[llvm] 3be9076 - [RISCV] Fix incorrect optimization for masked vmsgeu.vi with 0 immediate.
Zakk Chen via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 6 19:23:06 PST 2022
Author: Zakk Chen
Date: 2022-03-06T19:22:35-08:00
New Revision: 3be907621f158f3937e6a6c5fbf45a4b6cd6a414
URL: https://github.com/llvm/llvm-project/commit/3be907621f158f3937e6a6c5fbf45a4b6cd6a414
DIFF: https://github.com/llvm/llvm-project/commit/3be907621f158f3937e6a6c5fbf45a4b6cd6a414.diff
LOG: [RISCV] Fix incorrect optimization for masked vmsgeu.vi with 0 immediate.
vmsgeu.vi with 0 is always true, but in the masked with mask undisturbed
policy, we still need to keep inactive elelemt which come from maskedoff.
We could return mask directly if it's mask agnostic policy in the future.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D121080
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 93f093c93b94a..a15a6dd809b44 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1027,45 +1027,44 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
MVT Src1VT = Src1.getSimpleValueType();
unsigned VMSLTOpcode, VMSLTMaskOpcode, VMXOROpcode, VMANDNOpcode,
- VMSetOpcode, VMANDOpcode;
+ VMOROpcode;
switch (RISCVTargetLowering::getLMUL(Src1VT)) {
default:
llvm_unreachable("Unexpected LMUL!");
-#define CASE_VMSLT_VMSET_OPCODES(lmulenum, suffix, suffix_b) \
+#define CASE_VMSLT_OPCODES(lmulenum, suffix, suffix_b) \
case RISCVII::VLMUL::lmulenum: \
VMSLTOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix \
: RISCV::PseudoVMSLT_VX_##suffix; \
VMSLTMaskOpcode = IsUnsigned ? RISCV::PseudoVMSLTU_VX_##suffix##_MASK \
: RISCV::PseudoVMSLT_VX_##suffix##_MASK; \
- VMSetOpcode = RISCV::PseudoVMSET_M_##suffix_b; \
break;
- CASE_VMSLT_VMSET_OPCODES(LMUL_F8, MF8, B1)
- CASE_VMSLT_VMSET_OPCODES(LMUL_F4, MF4, B2)
- CASE_VMSLT_VMSET_OPCODES(LMUL_F2, MF2, B4)
- CASE_VMSLT_VMSET_OPCODES(LMUL_1, M1, B8)
- CASE_VMSLT_VMSET_OPCODES(LMUL_2, M2, B16)
- CASE_VMSLT_VMSET_OPCODES(LMUL_4, M4, B32)
- CASE_VMSLT_VMSET_OPCODES(LMUL_8, M8, B64)
-#undef CASE_VMSLT_VMSET_OPCODES
+ CASE_VMSLT_OPCODES(LMUL_F8, MF8, B1)
+ CASE_VMSLT_OPCODES(LMUL_F4, MF4, B2)
+ CASE_VMSLT_OPCODES(LMUL_F2, MF2, B4)
+ CASE_VMSLT_OPCODES(LMUL_1, M1, B8)
+ CASE_VMSLT_OPCODES(LMUL_2, M2, B16)
+ CASE_VMSLT_OPCODES(LMUL_4, M4, B32)
+ CASE_VMSLT_OPCODES(LMUL_8, M8, B64)
+#undef CASE_VMSLT_OPCODES
}
// Mask operations use the LMUL from the mask type.
switch (RISCVTargetLowering::getLMUL(VT)) {
default:
llvm_unreachable("Unexpected LMUL!");
-#define CASE_VMXOR_VMANDN_VMAND_OPCODES(lmulenum, suffix) \
+#define CASE_VMXOR_VMANDN_VMOR_OPCODES(lmulenum, suffix) \
case RISCVII::VLMUL::lmulenum: \
VMXOROpcode = RISCV::PseudoVMXOR_MM_##suffix; \
VMANDNOpcode = RISCV::PseudoVMANDN_MM_##suffix; \
- VMANDOpcode = RISCV::PseudoVMAND_MM_##suffix; \
+ VMOROpcode = RISCV::PseudoVMOR_MM_##suffix; \
break;
- CASE_VMXOR_VMANDN_VMAND_OPCODES(LMUL_F8, MF8)
- CASE_VMXOR_VMANDN_VMAND_OPCODES(LMUL_F4, MF4)
- CASE_VMXOR_VMANDN_VMAND_OPCODES(LMUL_F2, MF2)
- CASE_VMXOR_VMANDN_VMAND_OPCODES(LMUL_1, M1)
- CASE_VMXOR_VMANDN_VMAND_OPCODES(LMUL_2, M2)
- CASE_VMXOR_VMANDN_VMAND_OPCODES(LMUL_4, M4)
- CASE_VMXOR_VMANDN_VMAND_OPCODES(LMUL_8, M8)
-#undef CASE_VMXOR_VMANDN_VMAND_OPCODES
+ CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F8, MF8)
+ CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F4, MF4)
+ CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_F2, MF2)
+ CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_1, M1)
+ CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_2, M2)
+ CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_4, M4)
+ CASE_VMXOR_VMANDN_VMOR_OPCODES(LMUL_8, M8)
+#undef CASE_VMXOR_VMANDN_VMOR_OPCODES
}
SDValue SEW = CurDAG->getTargetConstant(
Log2_32(Src1VT.getScalarSizeInBits()), DL, XLenVT);
@@ -1075,12 +1074,17 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
SDValue MaskedOff = Node->getOperand(1);
SDValue Mask = Node->getOperand(4);
- // If vmsgeu_mask with 0 immediate, expand it to {vmset, vmand}.
+ // If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
if (IsCmpUnsignedZero) {
- SDValue VMSet =
- SDValue(CurDAG->getMachineNode(VMSetOpcode, DL, VT, VL, SEW), 0);
- ReplaceNode(Node, CurDAG->getMachineNode(VMANDOpcode, DL, VT,
- {Mask, VMSet, VL, MaskSEW}));
+ // We don't need vmor if the MaskedOff and the Mask are the same
+ // value.
+ if (Mask == MaskedOff) {
+ ReplaceUses(Node, Mask.getNode());
+ return;
+ }
+ ReplaceNode(Node,
+ CurDAG->getMachineNode(VMOROpcode, DL, VT,
+ {Mask, MaskedOff, VL, MaskSEW}));
return;
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
index 02750e7e4fff6..5ef098f08ea34 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
@@ -2097,9 +2097,8 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmset.m v8
-; CHECK-NEXT: vmand.mm v0, v9, v8
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmor.mm v0, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
@@ -2112,6 +2111,21 @@ entry:
ret <vscale x 2 x i1> %a
}
+define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
+ <vscale x 2 x i1> %0,
+ <vscale x 2 x i16> %1,
+ i16 0,
+ <vscale x 2 x i1> %0,
+ i32 %2)
+
+ ret <vscale x 2 x i1> %a
+}
+
define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
index c6c2daf8ed9c6..3030673621508 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll
@@ -2064,9 +2064,8 @@ entry:
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
-; CHECK-NEXT: vmset.m v8
-; CHECK-NEXT: vmand.mm v0, v9, v8
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vmor.mm v0, v9, v0
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
@@ -2094,6 +2093,21 @@ entry:
ret <vscale x 4 x i1> %a
}
+define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
+ <vscale x 2 x i1> %0,
+ <vscale x 2 x i16> %1,
+ i16 0,
+ <vscale x 2 x i1> %0,
+ i64 %2)
+
+ ret <vscale x 2 x i1> %a
+}
+
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
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