[PATCH] D121080: [RISCV] Fix incorrect optimization for masked vmsgeu.vi with 0 immediate.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1077
 
-      // If vmsgeu_mask with 0 immediate, expand it to {vmset, vmand}.
+      // If vmsgeu_mask with 0 immediate, expand it to vor mask, maskedoff.
       if (IsCmpUnsignedZero) {
----------------
vor -> vmor


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1079
       if (IsCmpUnsignedZero) {
-        SDValue VMSet =
-            SDValue(CurDAG->getMachineNode(VMSetOpcode, DL, VT, VL, SEW), 0);
-        ReplaceNode(Node, CurDAG->getMachineNode(VMANDOpcode, DL, VT,
-                                                 {Mask, VMSet, VL, MaskSEW}));
+        // We don't need vor if the MaskedOff and the Mask are the same
+        // value.
----------------
vor -> vmor


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll:2114
 
+define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16_samm_mask_maskedoff(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16_samm_mask_maskedoff:
----------------
samm-> same?


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll:2096
 
+define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16_samm_mask_maskedoff(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16_samm_mask_maskedoff:
----------------
samm -> same?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D121080/new/

https://reviews.llvm.org/D121080