[llvm] 924eac4 - [Hexagon] Move single-use global tables into their only user and turn them into StringSwitch
Benjamin Kramer via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 6 10:27:37 PST 2022
Author: Benjamin Kramer
Date: 2022-03-06T19:23:09+01:00
New Revision: 924eac4942408fc0cd5490af76a6d23011a542d1
URL: https://github.com/llvm/llvm-project/commit/924eac4942408fc0cd5490af76a6d23011a542d1
DIFF: https://github.com/llvm/llvm-project/commit/924eac4942408fc0cd5490af76a6d23011a542d1.diff
LOG: [Hexagon] Move single-use global tables into their only user and turn them into StringSwitch
Delete the unused globals. NFCI.
Added:
Modified:
llvm/lib/Target/Hexagon/HexagonDepArch.h
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/lib/Target/Hexagon/HexagonSubtarget.h
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
Removed:
llvm/lib/Target/Hexagon/HexagonArch.h
################################################################################
diff --git a/llvm/lib/Target/Hexagon/HexagonArch.h b/llvm/lib/Target/Hexagon/HexagonArch.h
deleted file mode 100644
index 4a42ec98feb17..0000000000000
--- a/llvm/lib/Target/Hexagon/HexagonArch.h
+++ /dev/null
@@ -1,31 +0,0 @@
-//===- HexagonArch.h ------------------------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H
-#define LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H
-
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/Optional.h"
-#include "llvm/ADT/StringRef.h"
-#include "HexagonDepArch.h"
-#include <algorithm>
-
-namespace llvm {
-namespace Hexagon {
-
-template <class ArchCont, typename Val>
-llvm::Optional<ArchEnum> GetCpu(ArchCont const &ArchList, Val CPUString) {
- llvm::Optional<ArchEnum> Res;
- auto Entry = ArchList.find(CPUString);
- if (Entry != ArchList.end())
- Res = Entry->second;
- return Res;
-}
-} // namespace Hexagon
-} // namespace llvm
-#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H
diff --git a/llvm/lib/Target/Hexagon/HexagonDepArch.h b/llvm/lib/Target/Hexagon/HexagonDepArch.h
index 56174dc7e1362..41ce5c465d412 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepArch.h
+++ b/llvm/lib/Target/Hexagon/HexagonDepArch.h
@@ -12,82 +12,28 @@
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/BinaryFormat/ELF.h"
-
-#include <map>
-#include <string>
+#include "llvm/ADT/StringSwitch.h"
namespace llvm {
namespace Hexagon {
enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67, V68, V69 };
-static constexpr unsigned ArchValsNumArray[] = {5, 55, 60, 62, 65, 66, 67, 68, 69};
-static constexpr ArrayRef<unsigned> ArchValsNum(ArchValsNumArray);
-
-static constexpr StringLiteral ArchValsTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v68", "v69" };
-static constexpr ArrayRef<StringLiteral> ArchValsText(ArchValsTextArray);
-
-static constexpr StringLiteral CpuValsTextArray[] = { "hexagonv5", "hexagonv55", "hexagonv60", "hexagonv62", "hexagonv65", "hexagonv66", "hexagonv67", "hexagonv67t", "hexagonv68", "hexagonv69" };
-static constexpr ArrayRef<StringLiteral> CpuValsText(CpuValsTextArray);
-
-static constexpr StringLiteral CpuNickTextArray[] = { "v5", "v55", "v60", "v62", "v65", "v66", "v67", "v67t", "v68", "v69" };
-static constexpr ArrayRef<StringLiteral> CpuNickText(CpuNickTextArray);
-
-static const std::map<std::string, ArchEnum> CpuTable{
- {"generic", Hexagon::ArchEnum::V5},
- {"hexagonv5", Hexagon::ArchEnum::V5},
- {"hexagonv55", Hexagon::ArchEnum::V55},
- {"hexagonv60", Hexagon::ArchEnum::V60},
- {"hexagonv62", Hexagon::ArchEnum::V62},
- {"hexagonv65", Hexagon::ArchEnum::V65},
- {"hexagonv66", Hexagon::ArchEnum::V66},
- {"hexagonv67", Hexagon::ArchEnum::V67},
- {"hexagonv67t", Hexagon::ArchEnum::V67},
- {"hexagonv68", Hexagon::ArchEnum::V68},
- {"hexagonv69", Hexagon::ArchEnum::V69},
-};
-
-static const std::map<std::string, unsigned> ElfFlagsByCpuStr = {
- {"generic", llvm::ELF::EF_HEXAGON_MACH_V5},
- {"hexagonv5", llvm::ELF::EF_HEXAGON_MACH_V5},
- {"hexagonv55", llvm::ELF::EF_HEXAGON_MACH_V55},
- {"hexagonv60", llvm::ELF::EF_HEXAGON_MACH_V60},
- {"hexagonv62", llvm::ELF::EF_HEXAGON_MACH_V62},
- {"hexagonv65", llvm::ELF::EF_HEXAGON_MACH_V65},
- {"hexagonv66", llvm::ELF::EF_HEXAGON_MACH_V66},
- {"hexagonv67", llvm::ELF::EF_HEXAGON_MACH_V67},
- {"hexagonv67t", llvm::ELF::EF_HEXAGON_MACH_V67T},
- {"hexagonv68", llvm::ELF::EF_HEXAGON_MACH_V68},
- {"hexagonv69", llvm::ELF::EF_HEXAGON_MACH_V69},
-};
-static const std::map<unsigned, std::string> ElfArchByMachFlags = {
- {llvm::ELF::EF_HEXAGON_MACH_V5, "V5"},
- {llvm::ELF::EF_HEXAGON_MACH_V55, "V55"},
- {llvm::ELF::EF_HEXAGON_MACH_V60, "V60"},
- {llvm::ELF::EF_HEXAGON_MACH_V62, "V62"},
- {llvm::ELF::EF_HEXAGON_MACH_V65, "V65"},
- {llvm::ELF::EF_HEXAGON_MACH_V66, "V66"},
- {llvm::ELF::EF_HEXAGON_MACH_V67, "V67"},
- {llvm::ELF::EF_HEXAGON_MACH_V67T, "V67T"},
- {llvm::ELF::EF_HEXAGON_MACH_V68, "V68"},
- {llvm::ELF::EF_HEXAGON_MACH_V69, "V69"},
-};
-static const std::map<unsigned, std::string> ElfCpuByMachFlags = {
- {llvm::ELF::EF_HEXAGON_MACH_V5, "hexagonv5"},
- {llvm::ELF::EF_HEXAGON_MACH_V55, "hexagonv55"},
- {llvm::ELF::EF_HEXAGON_MACH_V60, "hexagonv60"},
- {llvm::ELF::EF_HEXAGON_MACH_V62, "hexagonv62"},
- {llvm::ELF::EF_HEXAGON_MACH_V65, "hexagonv65"},
- {llvm::ELF::EF_HEXAGON_MACH_V66, "hexagonv66"},
- {llvm::ELF::EF_HEXAGON_MACH_V67, "hexagonv67"},
- {llvm::ELF::EF_HEXAGON_MACH_V67T, "hexagonv67t"},
- {llvm::ELF::EF_HEXAGON_MACH_V68, "hexagonv68"},
- {llvm::ELF::EF_HEXAGON_MACH_V69, "hexagonv69"},
-};
-
+inline Optional<Hexagon::ArchEnum> getCpu(StringRef CPU) {
+ return StringSwitch<Optional<Hexagon::ArchEnum>>(CPU)
+ .Case("generic", Hexagon::ArchEnum::V5)
+ .Case("hexagonv5", Hexagon::ArchEnum::V5)
+ .Case("hexagonv55", Hexagon::ArchEnum::V55)
+ .Case("hexagonv60", Hexagon::ArchEnum::V60)
+ .Case("hexagonv62", Hexagon::ArchEnum::V62)
+ .Case("hexagonv65", Hexagon::ArchEnum::V65)
+ .Case("hexagonv66", Hexagon::ArchEnum::V66)
+ .Case("hexagonv67", Hexagon::ArchEnum::V67)
+ .Case("hexagonv67t", Hexagon::ArchEnum::V67)
+ .Case("hexagonv68", Hexagon::ArchEnum::V68)
+ .Case("hexagonv69", Hexagon::ArchEnum::V69)
+ .Default(None);
+}
} // namespace Hexagon
-} // namespace llvm;
+} // namespace llvm
#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index bdd2a2cfc5fa2..f8c5cddcb5a5e 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -95,8 +95,7 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU,
HexagonSubtarget &
HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
- Optional<Hexagon::ArchEnum> ArchVer =
- Hexagon::GetCpu(Hexagon::CpuTable, CPUString);
+ Optional<Hexagon::ArchEnum> ArchVer = Hexagon::getCpu(CPUString);
if (ArchVer)
HexagonArchVersion = *ArchVer;
else
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.h b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
index db682676cf125..f6c70928c2f6f 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.h
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.h
@@ -13,7 +13,7 @@
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H
-#include "HexagonArch.h"
+#include "HexagonDepArch.h"
#include "HexagonFrameLowering.h"
#include "HexagonISelLowering.h"
#include "HexagonInstrInfo.h"
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 9c095356396db..1a35bda2415dc 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -11,7 +11,7 @@
//===----------------------------------------------------------------------===//
#include "MCTargetDesc/HexagonMCTargetDesc.h"
-#include "HexagonArch.h"
+#include "HexagonDepArch.h"
#include "HexagonTargetStreamer.h"
#include "MCTargetDesc/HexagonInstPrinter.h"
#include "MCTargetDesc/HexagonMCAsmInfo.h"
@@ -410,8 +410,8 @@ std::string selectHexagonFS(StringRef CPU, StringRef FS) {
}
}
-static bool isCPUValid(const std::string &CPU) {
- return Hexagon::CpuTable.find(CPU) != Hexagon::CpuTable.cend();
+static bool isCPUValid(StringRef CPU) {
+ return Hexagon::getCpu(CPU).hasValue();
}
namespace {
@@ -560,12 +560,18 @@ void Hexagon_MC::addArchSubtarget(MCSubtargetInfo const *STI,
}
unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
- using llvm::Hexagon::ElfFlagsByCpuStr;
-
- const std::string CPU(STI.getCPU().str());
- auto F = ElfFlagsByCpuStr.find(CPU);
- assert(F != ElfFlagsByCpuStr.end() && "Unrecognized Architecture");
- return F->second;
+ return StringSwitch<unsigned>(STI.getCPU())
+ .Case("generic", llvm::ELF::EF_HEXAGON_MACH_V5)
+ .Case("hexagonv5", llvm::ELF::EF_HEXAGON_MACH_V5)
+ .Case("hexagonv55", llvm::ELF::EF_HEXAGON_MACH_V55)
+ .Case("hexagonv60", llvm::ELF::EF_HEXAGON_MACH_V60)
+ .Case("hexagonv62", llvm::ELF::EF_HEXAGON_MACH_V62)
+ .Case("hexagonv65", llvm::ELF::EF_HEXAGON_MACH_V65)
+ .Case("hexagonv66", llvm::ELF::EF_HEXAGON_MACH_V66)
+ .Case("hexagonv67", llvm::ELF::EF_HEXAGON_MACH_V67)
+ .Case("hexagonv67t", llvm::ELF::EF_HEXAGON_MACH_V67T)
+ .Case("hexagonv68", llvm::ELF::EF_HEXAGON_MACH_V68)
+ .Case("hexagonv69", llvm::ELF::EF_HEXAGON_MACH_V69);
}
llvm::ArrayRef<MCPhysReg> Hexagon_MC::GetVectRegRev() {
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