[PATCH] D120899: [RISCV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32

[Tintin via Phabricator via llvm-commits]

lhtin updated this revision to Diff 413221.
lhtin added a comment.

I fixed the extra bug found by the review and made some optimizations for the case where AVL is constant.
This is my first patch to the llvm project. Please feel free to point out any irregularities. Thanks.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120899/new/

https://reviews.llvm.org/D120899

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll

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