[llvm] 33b61c5 - [RISCV] Fix incorrect codegen introduced by D119688.
Zakk Chen via llvm-commits
llvm-commits at lists.llvm.org
Sat Mar 5 06:31:50 PST 2022
Author: Zakk Chen
Date: 2022-03-05T06:10:26-08:00
New Revision: 33b61c567883f81c97c26ccdb2afe405e4de794c
URL: https://github.com/llvm/llvm-project/commit/33b61c567883f81c97c26ccdb2afe405e4de794c
DIFF: https://github.com/llvm/llvm-project/commit/33b61c567883f81c97c26ccdb2afe405e4de794c.diff
LOG: [RISCV] Fix incorrect codegen introduced by D119688.
We should not emit a tail agnostic vlse for a tail undisturbed vmv.s.x
In D119688:
- if (IsScalarMove && !Node->getOperand(0).isUndef())
+ bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
+ if (HasPassthruOperand && !IsScalarMove &&
!Node->getOperand(0).isUndef())
break;
The IsScalarMove check in the if statement had been changed.
Differential Revision: https://reviews.llvm.org/D120963
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 0bb6ac8b7b011..93f093c93b94a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1633,7 +1633,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL ||
Node->getOpcode() == RISCVISD::VFMV_S_F_VL;
bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
- if (HasPassthruOperand && !IsScalarMove && !Node->getOperand(0).isUndef())
+ if (HasPassthruOperand && !Node->getOperand(0).isUndef())
break;
SDValue Src = HasPassthruOperand ? Node->getOperand(1) : Node->getOperand(0);
auto *Ld = dyn_cast<LoadSDNode>(Src);
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
index 3472a83e0ff4f..3d876dc257ddd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
@@ -291,8 +291,9 @@ entry:
define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64_bug(<vscale x 1 x i64> %0, i64* %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64_bug:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vlse64.v v8, (a0), zero
+; CHECK-NEXT: ld a0, 0(a0)
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, tu, mu
+; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
entry:
%a = load i64, i64* %1, align 8
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