[llvm] 1e569e3 - [RISCV] Add CMOV isel pattern for (select (setgt X, -1), Y, Z)

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-03-04T22:35:13-08:00
New Revision: 1e569e3b7b594f1e69dc5963b6ee4d821e7c68fb

URL: https://github.com/llvm/llvm-project/commit/1e569e3b7b594f1e69dc5963b6ee4d821e7c68fb
DIFF: https://github.com/llvm/llvm-project/commit/1e569e3b7b594f1e69dc5963b6ee4d821e7c68fb.diff

LOG: [RISCV] Add CMOV isel pattern for (select (setgt X, -1), Y, Z)

setgt X, -1 is the canonical form of setge X, 0. We can swap the
select operands and use setlt X, X0 when selecting CMOV. This
avoid materializing the -1 in a register.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/test/CodeGen/RISCV/select-cc.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index c6c564175cd2b..16087150fba87 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -963,6 +963,12 @@ def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
+
+// setge X, 0 is canonicalized to setgt X, -1.
+// FIXME: This can be generalized to more immediates by using SLTI.
+def : Pat<(select (XLenVT (setgt GPR:$x, -1)), GPR:$rs3, GPR:$rs1),
+          (CMOV GPR:$rs1, (SLT GPR:$x, X0), GPR:$rs3)>;
+
 def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 } // Predicates = [HasStdExtZbt]

diff  --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index 5150f4ed70990..32afdabe192f1 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -98,16 +98,15 @@ define signext i32 @foo(i32 signext %a, i32 *%b) nounwind {
 ; RV32IBT-NEXT:    cmov a0, a4, a3, a0
 ; RV32IBT-NEXT:    lw a3, 0(a1)
 ; RV32IBT-NEXT:    slt a4, a0, a2
-; RV32IBT-NEXT:    lw a5, 0(a1)
 ; RV32IBT-NEXT:    cmov a0, a4, a0, a2
-; RV32IBT-NEXT:    slt a2, a3, a0
-; RV32IBT-NEXT:    cmov a0, a2, a3, a0
-; RV32IBT-NEXT:    slti a2, a5, 1
+; RV32IBT-NEXT:    lw a2, 0(a1)
+; RV32IBT-NEXT:    slt a4, a3, a0
+; RV32IBT-NEXT:    cmov a0, a4, a3, a0
 ; RV32IBT-NEXT:    lw a1, 0(a1)
-; RV32IBT-NEXT:    cmov a0, a2, a0, a5
-; RV32IBT-NEXT:    li a2, -1
-; RV32IBT-NEXT:    slt a2, a2, a5
-; RV32IBT-NEXT:    cmov a0, a2, a0, a1
+; RV32IBT-NEXT:    slti a3, a2, 1
+; RV32IBT-NEXT:    cmov a0, a3, a0, a2
+; RV32IBT-NEXT:    sltz a2, a2
+; RV32IBT-NEXT:    cmov a0, a2, a1, a0
 ; RV32IBT-NEXT:    ret
   %val1 = load volatile i32, i32* %b
   %tst1 = icmp eq i32 %a, %val1