[llvm] dce6aa2 - [NVPTX] Correctly set regs for neg, abs intrinsics

Artem Belevich via llvm-commits llvm-commits at lists.llvm.org
Fri Mar 4 11:07:19 PST 2022


Author: Jakub Chlanda
Date: 2022-03-04T11:06:07-08:00
New Revision: dce6aa237a07e581881f540222e68e6f2b912430

URL: https://github.com/llvm/llvm-project/commit/dce6aa237a07e581881f540222e68e6f2b912430
DIFF: https://github.com/llvm/llvm-project/commit/dce6aa237a07e581881f540222e68e6f2b912430.diff

LOG: [NVPTX] Correctly set regs for neg, abs intrinsics

This patch fixes a bug introduced in D117887.

Reviewed By: tra

Differential Revision: https://reviews.llvm.org/D120991

Added: 
    

Modified: 
    llvm/lib/Target/NVPTX/NVPTXIntrinsics.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
index 9cf4153172723..176ba20972af6 100644
--- a/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
+++ b/llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
@@ -855,13 +855,13 @@ def INT_NVVM_FABS_D : F_MATH_1<"abs.f64 \t$dst, $src0;", Float64Regs,
 // Abs, Neg bf16, bf16x2
 //
 
-def INT_NVVM_ABS_BF16 : F_MATH_1<"abs.bf16 \t$dst, $dst;", Int16Regs,
+def INT_NVVM_ABS_BF16 : F_MATH_1<"abs.bf16 \t$dst, $src0;", Int16Regs,
   Int16Regs, int_nvvm_abs_bf16, [hasPTX70, hasSM80]>;
-def INT_NVVM_ABS_BF16X2 : F_MATH_1<"abs.bf16x2 \t$dst, $dst;", Int32Regs,
+def INT_NVVM_ABS_BF16X2 : F_MATH_1<"abs.bf16x2 \t$dst, $src0;", Int32Regs,
   Int32Regs, int_nvvm_abs_bf16x2, [hasPTX70, hasSM80]>;
-def INT_NVVM_NEG_BF16 : F_MATH_1<"neg.bf16 \t$dst, $dst;", Int16Regs,
+def INT_NVVM_NEG_BF16 : F_MATH_1<"neg.bf16 \t$dst, $src0;", Int16Regs,
   Int16Regs, int_nvvm_neg_bf16, [hasPTX70, hasSM80]>;
-def INT_NVVM_NEG_BF16X2 : F_MATH_1<"neg.bf16x2 \t$dst, $dst;", Int32Regs,
+def INT_NVVM_NEG_BF16X2 : F_MATH_1<"neg.bf16x2 \t$dst, $src0;", Int32Regs,
   Int32Regs, int_nvvm_neg_bf16x2, [hasPTX70, hasSM80]>;
 
 //


        


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