[PATCH] D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users.

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp:1602
   unsigned OpIdx = Op - &UseMI->getOperand(0);
+  if (TII->isUnknownRegClass(*UseMI, OpIdx))
+    return false;
----------------
foad wrote:
> cdevadas wrote:
> > foad wrote:
> > > You could just use TargetInstrInfo::getRegClass(InstDesc, OpIdx, TRI, MF) instead of TRI->getRegClass and it would do all these checks for you already.
> > We can't use that equivalent of `getRegClass` here. The call to `adjustAllocatableRegClass` inside it would change AV classes to V thereby disabling the folding in almost all valid cases.
> > 
> The call to `adjustAllocatableRegClass` is in the AMDGPU-specific getOpRegClass, not in the generic getRegClass.
@foad thanks for pointing that generic function.

We have some variants in SIInstrInfo.cpp to get regclass value from InstDesc.
I initially tried to use SIInstrInfo::getOpRegClass(const MachineInstr &MI, unsigned OpNo) and found the `adjustAllocatableRegClass` calls inside it prevented the folding for some tests involving loads and stores.

But SIInstrInfo::getRegClass(InstDesc, OpIdx, TRI, MF) seems to be working. Though it also has a call to `adjustAllocatableRegClass`, it is more restrained and appeared to be not missing any folding opportunity for loads/stores that failed earlier with the other variant.
I am going to use this function. Will update the patch.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D120813/new/

https://reviews.llvm.org/D120813