[PATCH] D120891: [AArch64] Perform first active true vector combine

Fri Mar 4 03:13:45 PST 2022

david-arm added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/sve-extract-element.ll:486
+; CHECK-NEXT:    ptest p1, p0.b
+; CHECK-NEXT:    cset w0, mi
 ; CHECK-NEXT:    ret
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To be honest, this doesn't look like a win to me. We're introducing control flow where previously we had none. I think we should avoid setting the flags when the original code set none.

I think I'd prefer it if you restricted the DAG combine to only cases where we're extracting from a flag-setting operation, i.e. an extract from a icmp.

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Comment at: llvm/test/CodeGen/AArch64/sve-pture.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -o - %s | FileCheck  %s
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Maybe this is better in something like sve-cmp-folds.ll?

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Comment at: llvm/test/CodeGen/AArch64/sve-pture.ll:51
+  %predicate.next = icmp ult <vscale x 4 x i64> %1, %step
+  %test0 = extractelement <vscale x 4 x i1> %predicate.next, i64 0
+  br i1 %test0, label %vector.body, label %cleanup
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This looks quite an odd IR sequence and I don't think will ever be generated by the vectoriser. I imagine this has come from hand-written SVE ACLE code.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120891/new/

https://reviews.llvm.org/D120891