[PATCH] D120963: [RISCV] Fix incorrect codegen introduced by D119688.
Zakk Chen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Mar 3 19:57:07 PST 2022
khchen created this revision.
khchen added reviewers: craig.topper, rogfer01, frasercrmck, kito-cheng.
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We should not emit a tail agnostic vlse for a tail undisturbed vmv.s.x
In D119688 <https://reviews.llvm.org/D119688>:
- if (IsScalarMove && !Node->getOperand(0).isUndef())
+ bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
+ if (HasPassthruOperand && !IsScalarMove &&
!Node->getOperand(0).isUndef())
break;
The IsScalarMove check in the if statement had been changed.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D120963
Files:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
Index: llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
@@ -291,8 +291,9 @@
define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64_bug(<vscale x 1 x i64> %0, i64* %1) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64_bug:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, mu
-; CHECK-NEXT: vlse64.v v8, (a0), zero
+; CHECK-NEXT: ld a0, 0(a0)
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, tu, mu
+; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret
entry:
%a = load i64, i64* %1, align 8
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1633,7 +1633,7 @@
bool IsScalarMove = Node->getOpcode() == RISCVISD::VMV_S_X_VL ||
Node->getOpcode() == RISCVISD::VFMV_S_F_VL;
bool HasPassthruOperand = Node->getOpcode() != ISD::SPLAT_VECTOR;
- if (HasPassthruOperand && !IsScalarMove && !Node->getOperand(0).isUndef())
+ if (HasPassthruOperand && !Node->getOperand(0).isUndef())
break;
SDValue Src = HasPassthruOperand ? Node->getOperand(1) : Node->getOperand(0);
auto *Ld = dyn_cast<LoadSDNode>(Src);
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