[PATCH] D120912: [AArch64][SVE] Convert gather/scatter with a stride of 2 to contiguous loads/stores

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Did you try using ld2/st2?  I guess the problem is that it accesses too many bytes?



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16628
+  if (Index->getOpcode() == ISD::STEP_VECTOR &&
+      Mask->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
+      IndexType == ISD::SIGNED_SCALED) {
----------------
Why the restriction on the mask opcode?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16646
+    default:
+      return SDValue();
+    }
----------------
I guess you're not handling i16/i8 because you'd have to worry about extension?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120912/new/

https://reviews.llvm.org/D120912