[PATCH] D120813: AMDGPU: Skip folding REG_SEQUENCE if found unknown regclasses for its users.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4761
+  const MCInstrDesc &Desc = get(MI.getOpcode());
+  if (MI.isVariadic() || OpIdx >= Desc.getNumOperands() ||
+      Desc.OpInfo[OpIdx].RegClass == -1)
----------------
cdevadas wrote:
> foad wrote:
> > Why do you need to test isVariadic here()? Surely as long as you compare OpIdx against Desc.getNumOperands() (not MI.getNumOperands()) you're OK?
> No, `OpIdx >= Desc.getNumOperands()` didn't hold true when I checked the case REG_SEQUENCE (REG_SEQUENCE). Is it because the passed Op index is already adjusted from `UseMI->getOperand(0)`?
Even variadic instructions shall have proper operand description before the variadic part starts.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120813/new/

https://reviews.llvm.org/D120813