[PATCH] D120597: [RISCV] With Zbb, fold (sext_inreg (abs X)) -> (max X, (negw X))

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7541
+      cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32 &&
+      DAG.ComputeNumSignBits(Src.getOperand(0)) > 32) {
+    SDLoc DL(N);
----------------
craig.topper wrote:
> spatel wrote:
> > Can the `ComputeNumSignBits` be an assert rather than part of the predicate?
> The input is sign extended if the abs was promoted by type legalization, but I think it is possible to write (i64 (sext (i32 (trunc (i64 abs X)))) in the original IR and the input would not be sign extended.
Maybe I'm not understanding the pattern - is it possible to write a negative test?
If we sext_inreg from i32, does this model the transform:
https://alive2.llvm.org/ce/z/j4RdVa ?


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