[PATCH] D120899: [RISCV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32

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When left-shifting the incoming VL parameter, it may cause overflow
when the vl >= 0x80000000, resulting in the wrong VL length setting.
For example this code and the output:

  #include <riscv_vector.h>
  
  vint64m1_t
  test (vint64m1_t a, int64_t b)
  {
      return vslide1up_vx_i64m1(a, b, 0x80000000);
  }
  /* assembly output:
  test: 
          vsetivli        zero, 0, e32, m1, ta, mu
          vslide1up.vx    v9, v8, a1
          vslide1up.vx    v8, v9, a0
          ret
  */

The bug was caused by this commit <https://reviews.llvm.org/D99910>


https://reviews.llvm.org/D120899

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/masked-vslide1down-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll

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