[PATCH] D120597: [RISCV] With Zbb, fold (sext_inreg (abs X)) -> (max X, (negw X))

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7541
+      cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32 &&
+      DAG.ComputeNumSignBits(Src.getOperand(0)) > 32) {
+    SDLoc DL(N);
----------------
Can the `ComputeNumSignBits` be an assert rather than part of the predicate?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7544-7548
+    SDValue Neg =
+        DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Freeze);
+    Neg = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Neg,
+                      DAG.getValueType(MVT::i32));
+    return DAG.getNode(ISD::SMAX, DL, VT, Freeze, Neg);
----------------
If this will never be anything but a quirk of the i64 type, replace `VT` with `MVT::i64` to make that clearer?


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  https://reviews.llvm.org/D120597/new/

https://reviews.llvm.org/D120597