[PATCH] D120895: Tail calls: look through AssertZExt to find register copy.

[Tim Northover via Phabricator via llvm-commits]

t.p.northover created this revision.
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arm64_32 guarantees the high 32 bits of pointer parameters are passed as 0, and this is modelled in the IR by inserting an AssertZExt after the copyFromReg. The function deciding whether registers that need to be preserved actually are wasn't expecting this so it banned perfectly legitimate tail calls.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120895

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/swiftself.ll


Index: llvm/test/CodeGen/AArch64/swiftself.ll
===================================================================
--- llvm/test/CodeGen/AArch64/swiftself.ll
+++ llvm/test/CodeGen/AArch64/swiftself.ll
@@ -51,10 +51,10 @@
 ; CHECK-LABEL: swiftself_tail:
 ; OPTAARCH64: b {{_?}}swiftself_param
 ; OPTAARCH64-NOT: ret
-; OPTARM64_32: bl {{_?}}swiftself_param
+; OPTARM64_32: b {{_?}}swiftself_param
 define i8* @swiftself_tail(i8* swiftself %addr0) {
   call void asm sideeffect "", "~{x20}"()
-  %res = tail call i8* @swiftself_param(i8* swiftself %addr0)
+  %res = musttail call i8* @swiftself_param(i8* swiftself %addr0)
   ret i8* %res
 }
 
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -94,6 +94,8 @@
     // (We look for a CopyFromReg reading a virtual register that is used
     //  for the function live-in value of register Reg)
     SDValue Value = OutVals[I];
+    if (Value->getOpcode() == ISD::AssertZext)
+      Value = Value.getOperand(0);
     if (Value->getOpcode() != ISD::CopyFromReg)
       return false;
     Register ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();


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