[llvm] 1cfcbf1 - [PowerPC][atomics] Precommit test cases for i128 cmpxchg. NFC.

[Kai Luo via llvm-commits]

Author: Kai Luo
Date: 2022-03-03T10:47:52+08:00
New Revision: 1cfcbf197cf61e7b9d0669d9b3450caed2494e6d

URL: https://github.com/llvm/llvm-project/commit/1cfcbf197cf61e7b9d0669d9b3450caed2494e6d
DIFF: https://github.com/llvm/llvm-project/commit/1cfcbf197cf61e7b9d0669d9b3450caed2494e6d.diff

LOG: [PowerPC][atomics] Precommit test cases for i128 cmpxchg. NFC.

Added: 
    llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll

Modified: 
    llvm/test/CodeGen/PowerPC/atomics-i128.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/PowerPC/atomics-i128.ll b/llvm/test/CodeGen/PowerPC/atomics-i128.ll
index 9647288ea6bce..75466a2f87998 100644
--- a/llvm/test/CodeGen/PowerPC/atomics-i128.ll
+++ b/llvm/test/CodeGen/PowerPC/atomics-i128.ll
@@ -450,3 +450,65 @@ entry:
   %1 = extractvalue { i128, i1 } %0, 0
   ret i128 %1
 }
+
+define i1 @cas_acqrel_acquire_check_succ(i128* %a, i128 %cmp, i128 %new) {
+; CHECK-LABEL: cas_acqrel_acquire_check_succ:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lwsync
+; CHECK-NEXT:  .LBB11_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lqarx r8, 0, r3
+; CHECK-NEXT:    xor r11, r9, r5
+; CHECK-NEXT:    xor r10, r8, r4
+; CHECK-NEXT:    or. r11, r11, r10
+; CHECK-NEXT:    bne cr0, .LBB11_3
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    mr r11, r7
+; CHECK-NEXT:    mr r10, r6
+; CHECK-NEXT:    stqcx. r10, 0, r3
+; CHECK-NEXT:    bne cr0, .LBB11_1
+; CHECK-NEXT:    b .LBB11_4
+; CHECK-NEXT:  .LBB11_3: # %entry
+; CHECK-NEXT:    stqcx. r8, 0, r3
+; CHECK-NEXT:  .LBB11_4: # %entry
+; CHECK-NEXT:    lwsync
+; CHECK-NEXT:    xor r3, r5, r9
+; CHECK-NEXT:    or r3, r3, r4
+; CHECK-NEXT:    cntlzd r3, r3
+; CHECK-NEXT:    rldicl r3, r3, 58, 63
+; CHECK-NEXT:    blr
+;
+; PWR7-LABEL: cas_acqrel_acquire_check_succ:
+; PWR7:       # %bb.0: # %entry
+; PWR7-NEXT:    mflr r0
+; PWR7-NEXT:    std r0, 16(r1)
+; PWR7-NEXT:    stdu r1, -144(r1)
+; PWR7-NEXT:    .cfi_def_cfa_offset 144
+; PWR7-NEXT:    .cfi_offset lr, 16
+; PWR7-NEXT:    .cfi_offset r29, -24
+; PWR7-NEXT:    .cfi_offset r30, -16
+; PWR7-NEXT:    std r29, 120(r1) # 8-byte Folded Spill
+; PWR7-NEXT:    std r30, 128(r1) # 8-byte Folded Spill
+; PWR7-NEXT:    mr r30, r5
+; PWR7-NEXT:    mr r29, r4
+; PWR7-NEXT:    lwsync
+; PWR7-NEXT:    bl __sync_val_compare_and_swap_16
+; PWR7-NEXT:    nop
+; PWR7-NEXT:    xor r3, r3, r29
+; PWR7-NEXT:    xor r4, r4, r30
+; PWR7-NEXT:    lwsync
+; PWR7-NEXT:    or r3, r4, r3
+; PWR7-NEXT:    ld r30, 128(r1) # 8-byte Folded Reload
+; PWR7-NEXT:    ld r29, 120(r1) # 8-byte Folded Reload
+; PWR7-NEXT:    cntlzd r3, r3
+; PWR7-NEXT:    rldicl r3, r3, 58, 63
+; PWR7-NEXT:    addi r1, r1, 144
+; PWR7-NEXT:    ld r0, 16(r1)
+; PWR7-NEXT:    mtlr r0
+; PWR7-NEXT:    blr
+entry:
+  %0 = cmpxchg i128* %a, i128 %cmp, i128 %new acq_rel acquire
+  %1 = extractvalue { i128, i1 } %0, 1
+  ret i1 %1
+}

diff  --git a/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
new file mode 100644
index 0000000000000..e1cbcd3fcf2d6
--- /dev/null
+++ b/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -atomic-expand -S -mtriple=powerpc64-unknown-unknown \
+; RUN:   -ppc-quadword-atomics -mcpu=pwr8 %s | FileCheck %s
+
+define i1 @test_cmpxchg_seq_cst(i128* %addr, i128 %desire, i128 %new) {
+; CHECK-LABEL: @test_cmpxchg_seq_cst(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMPVAL_SHIFTED:%.*]] = shl i128 [[DESIRE:%.*]], 0
+; CHECK-NEXT:    [[NEWVAL_SHIFTED:%.*]] = shl i128 [[NEW:%.*]], 0
+; CHECK-NEXT:    [[CMP_LO:%.*]] = trunc i128 [[CMPVAL_SHIFTED]] to i64
+; CHECK-NEXT:    [[TMP0:%.*]] = lshr i128 [[CMPVAL_SHIFTED]], 64
+; CHECK-NEXT:    [[CMP_HI:%.*]] = trunc i128 [[TMP0]] to i64
+; CHECK-NEXT:    [[NEW_LO:%.*]] = trunc i128 [[NEWVAL_SHIFTED]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i128 [[NEWVAL_SHIFTED]], 64
+; CHECK-NEXT:    [[NEW_HI:%.*]] = trunc i128 [[TMP1]] to i64
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i128* [[ADDR:%.*]] to i8*
+; CHECK-NEXT:    call void @llvm.ppc.sync()
+; CHECK-NEXT:    [[TMP3:%.*]] = call { i64, i64 } @llvm.ppc.cmpxchg.i128(i8* [[TMP2]], i64 [[CMP_LO]], i64 [[CMP_HI]], i64 [[NEW_LO]], i64 [[NEW_HI]])
+; CHECK-NEXT:    call void @llvm.ppc.lwsync()
+; CHECK-NEXT:    [[LO:%.*]] = extractvalue { i64, i64 } [[TMP3]], 0
+; CHECK-NEXT:    [[HI:%.*]] = extractvalue { i64, i64 } [[TMP3]], 1
+; CHECK-NEXT:    [[LO64:%.*]] = zext i64 [[LO]] to i128
+; CHECK-NEXT:    [[HI64:%.*]] = zext i64 [[HI]] to i128
+; CHECK-NEXT:    [[TMP4:%.*]] = shl i128 [[HI64]], 64
+; CHECK-NEXT:    [[VAL64:%.*]] = or i128 [[LO64]], [[TMP4]]
+; CHECK-NEXT:    [[TMP5:%.*]] = insertvalue { i128, i1 } undef, i128 [[VAL64]], 0
+; CHECK-NEXT:    [[TMP6:%.*]] = and i128 [[VAL64]], 18446744073709551615
+; CHECK-NEXT:    [[SUCCESS:%.*]] = icmp eq i128 [[CMPVAL_SHIFTED]], [[TMP6]]
+; CHECK-NEXT:    [[TMP7:%.*]] = insertvalue { i128, i1 } [[TMP5]], i1 [[SUCCESS]], 1
+; CHECK-NEXT:    [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP7]], 1
+; CHECK-NEXT:    ret i1 [[SUCC]]
+;
+entry:
+  %pair = cmpxchg weak i128* %addr, i128 %desire, i128 %new seq_cst seq_cst
+  %succ = extractvalue {i128, i1} %pair, 1
+  ret i1 %succ
+}