[PATCH] D120592: [X86] Preserve redundant Address-Size override prefix
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Mar 2 15:56:22 PST 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp:75
+bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) {
+ const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg);
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Missing namespace? Or missing `static`?
================
Comment at: llvm/test/MC/X86/index-operations.s:74
stos %rax, (%edi)
-// 64: stosq %rax, %es:(%edi) # encoding: [0x48,0x67,0xab]
// ERR32: only available in 64-bit mode
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Was this a bug before? REX prefix is supposed to be the byte before the opcode.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D120592/new/
https://reviews.llvm.org/D120592
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