[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

Jessica Clarke via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Mar 2 11:41:28 PST 2022

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jrtc27 added a comment.

Does a double with `r` for RV32 work with that fix? That's supposed to give the low half of the register. You might need to also deal with the register pair class?


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

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