[PATCH] D120813: AMDGPU: Skip tryFoldRegSequence if no valid regclasses for its users.

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added a comment.

In D120813#3354292 <https://reviews.llvm.org/D120813#3354292>, @arsenm wrote:

> What's the reasoning for this? Won't this break chains of REG_SEQUENCE? In particular I do expect to see some REG_SEQUENCE (REG_SEQUENCE), (REG_SEQUENCE) patterns

Currently skipping it to avoid a crash that occurred with REG_SEQUENCE(REG_SEQUENCE) while trying to look for the regclass @OpIdx from the UseMI's MCInstrDesc.
These special cases involving target-independent and/or variadic instructions should be handled separately.
This folding will take place only when the regclass at OpIdx is a vectorSuperClass https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp#L1603
Currently, we don't select any AV operands and I guess it is ok to skip them.



================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4758
 
+bool SIInstrInfo::isVariadicOrInvalidRegClassAtOpIdx(const MachineInstr &MI,
+                                                     unsigned OpIdx) const {
----------------
arsenm wrote:
> isUnknownRegClass?
Will use


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:4761
+  const MCInstrDesc &Desc = get(MI.getOpcode());
+  if (MI.isVariadic() || OpIdx >= Desc.getNumOperands() ||
+      Desc.OpInfo[OpIdx].RegClass == -1)
----------------
foad wrote:
> Why do you need to test isVariadic here()? Surely as long as you compare OpIdx against Desc.getNumOperands() (not MI.getNumOperands()) you're OK?
No, `OpIdx >= Desc.getNumOperands()` didn't hold true when I checked the case REG_SEQUENCE (REG_SEQUENCE). Is it because the passed Op index is already adjusted from `UseMI->getOperand(0)`?


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https://reviews.llvm.org/D120813