[PATCH] D120761: [SelectionDAG][RISCV] Emit a canonical sign bit test from ExpandIntRes_ABS.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Instead of emitting 0 > Hi, emit Hi < 0. If Hi needs to be expanded again
this will allow the special case for sign bit tests in ExpandIntOp_SETCC
to trigger.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120761

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/RISCV/iabs.ll

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