[llvm] c752eb4 - [RISCV] Add test cases miscompile of (rotl (grevi X, 24), 16) on RV64. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-03-01T07:32:07-08:00
New Revision: c752eb4ae19710983500eef963e258b207e42df0

URL: https://github.com/llvm/llvm-project/commit/c752eb4ae19710983500eef963e258b207e42df0
DIFF: https://github.com/llvm/llvm-project/commit/c752eb4ae19710983500eef963e258b207e42df0.diff

LOG: [RISCV] Add test cases miscompile of (rotl (grevi X, 24), 16) on RV64. NFC

This pattern was moved from isel to DAG combine in D119527, but
it lost the RV32 qualification in the process.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
index fc1aa711d7421..c8065affadc79 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
@@ -340,6 +340,30 @@ define i64 @grevi64(i64 %a) nounwind {
  ret i64 %tmp
 }
 
+; FIXME: This is miscompiled. We can't fold the rotate with the grev.
+define i64 @grevi64_24_rotl_16(i64 %a) nounwind {
+; RV64ZBP-LABEL: grevi64_24_rotl_16:
+; RV64ZBP:       # %bb.0:
+; RV64ZBP-NEXT:    rev8.h a0, a0
+; RV64ZBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 24)
+  %tmp1 = call i64 @llvm.fshl.i64(i64 %tmp, i64 %tmp, i64 16)
+ ret i64 %tmp1
+}
+declare i64 @llvm.fshl.i64(i64, i64, i64)
+
+; FIXME: This is miscompiled. We can't fold the rotate with the grev.
+define i64 @grevi64_24_rotr_16(i64 %a) nounwind {
+; RV64ZBP-LABEL: grevi64_24_rotr_16:
+; RV64ZBP:       # %bb.0:
+; RV64ZBP-NEXT:    rev8.h a0, a0
+; RV64ZBP-NEXT:    ret
+  %tmp = call i64 @llvm.riscv.grev.i64(i64 %a, i64 24)
+  %tmp1 = call i64 @llvm.fshr.i64(i64 %tmp, i64 %tmp, i64 16)
+ ret i64 %tmp1
+}
+declare i64 @llvm.fshr.i64(i64, i64, i64)
+
 define i64 @revhwi64(i64 %a) nounwind {
 ; RV64ZBP-LABEL: revhwi64:
 ; RV64ZBP:       # %bb.0: