[PATCH] D119303: [RISCV] Lower VECTOR_SPLICE to RVV instructions.
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 1 07:23:50 PST 2022
frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.
LGTM, sorry for the delay.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vector-splice.ll:4
+
+; Tests assume VLEN=128 or vscale_range_min=2.
+
----------------
craig.topper wrote:
> frasercrmck wrote:
> > Do they?
> There's a verifier check on the range of the immediate. Without a vscale_range the only allowed constants for <vscale x 1 x *> are 0 and -1. So I increased it to give more options.
Ah I see, thanks, that wasn't obvious.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D119303/new/
https://reviews.llvm.org/D119303
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