[PATCH] D120709: [AMDGPU] Preserve src2_modifiers in convertToThreeAddress

[Jay Foad via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG68895098d11f: [AMDGPU] Preserve src2_modifiers in convertToThreeAddress (authored by foad).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120709/new/

https://reviews.llvm.org/D120709

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
  llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir


Index: llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
+++ llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
@@ -232,9 +232,8 @@
     %3:vgpr_32 = V_MAC_F32_e64 0, %0, 1, %1, 0, %2, 0, 0, implicit $mode, implicit $exec
 ...
 
-# FIXME: Preserve src2_modifiers
 # GCN-LABEL: name: test_mad_src2mods
-# GCN: %3:vgpr_32 = V_MAD_F32_e64 0, %0, 0, %1, 0, %2, 0, 0, implicit $mode, implicit $exec
+# GCN: %3:vgpr_32 = V_MAD_F32_e64 0, %0, 0, %1, 1, %2, 0, 0, implicit $mode, implicit $exec
 ---
 name: test_mad_src2mods
 body: |
Index: llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
+++ llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
@@ -297,9 +297,8 @@
     %3:vgpr_32 = V_FMAC_F32_e64 0, %0, 1, %1, 0, %2, 0, 0, implicit $mode, implicit $exec
 ...
 
-# FIXME: Preserve src2_modifiers
 # GCN-LABEL: name: test_fma_src2mods
-# GCN: %3:vgpr_32 = V_FMA_F32_e64 0, %0, 0, %1, 0, %2, 0, 0, implicit $mode, implicit $exec
+# GCN: %3:vgpr_32 = V_FMA_F32_e64 0, %0, 0, %1, 1, %2, 0, 0, implicit $mode, implicit $exec
 ---
 name: test_fma_src2mods
 body: |
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3289,10 +3289,12 @@
   const MachineOperand *Src1Mods =
     getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
   const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
+  const MachineOperand *Src2Mods =
+      getNamedOperand(MI, AMDGPU::OpName::src2_modifiers);
   const MachineOperand *Clamp = getNamedOperand(MI, AMDGPU::OpName::clamp);
   const MachineOperand *Omod = getNamedOperand(MI, AMDGPU::OpName::omod);
 
-  if (!Src0Mods && !Src1Mods && !Clamp && !Omod && !IsF64 &&
+  if (!Src0Mods && !Src1Mods && !Src2Mods && !Clamp && !Omod && !IsF64 &&
       // If we have an SGPR input, we will violate the constant bus restriction.
       (ST.getConstantBusLimit(Opc) > 1 || !Src0->isReg() ||
        !RI.isSGPRReg(MBB.getParent()->getRegInfo(), Src0->getReg()))) {
@@ -3375,7 +3377,7 @@
             .add(*Src0)
             .addImm(Src1Mods ? Src1Mods->getImm() : 0)
             .add(*Src1)
-            .addImm(0) // Src mods
+            .addImm(Src2Mods ? Src2Mods->getImm() : 0)
             .add(*Src2)
             .addImm(Clamp ? Clamp->getImm() : 0)
             .addImm(Omod ? Omod->getImm() : 0);


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