[llvm] 70c398c - [AArch64] Use common CHECK prefix for test, reducing duplicated checks.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 1 02:30:50 PST 2022
Author: Florian Hahn
Date: 2022-03-01T10:30:29Z
New Revision: 70c398c198135ca9b3a959efd7512a4df8369e4a
URL: https://github.com/llvm/llvm-project/commit/70c398c198135ca9b3a959efd7512a4df8369e4a
DIFF: https://github.com/llvm/llvm-project/commit/70c398c198135ca9b3a959efd7512a4df8369e4a.diff
LOG: [AArch64] Use common CHECK prefix for test, reducing duplicated checks.
Use the common CHECK prefix with runlines with and without fullfp16.
This means no duplicated checks are generated for tests not using fp16.
Added:
Modified:
llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/vecreduce-fadd.ll b/llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
index 4ccf170c32b57..c8daed63fe93c 100644
--- a/llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
+++ b/llvm/test/CodeGen/AArch64/vecreduce-fadd.ll
@@ -1,27 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=aarch64-eabi -aarch64-neon-syntax=generic -mattr=+fullfp16 < %s | FileCheck %s
-; RUN: llc --mtriple=aarch64-eabi -aarch64-neon-syntax=generic < %s | FileCheck %s --check-prefix=CHECKNOFP16
+; RUN: llc --mtriple=aarch64-eabi -aarch64-neon-syntax=generic -mattr=+fullfp16 < %s | FileCheck --check-prefixes=CHECK,FULLFP16 %s
+; RUN: llc --mtriple=aarch64-eabi -aarch64-neon-syntax=generic < %s | FileCheck %s --check-prefixes=CHECK,CHECKNOFP16
define float @add_HalfS(<2 x float> %bin.rdx) {
; CHECK-LABEL: add_HalfS:
; CHECK: // %bb.0:
; CHECK-NEXT: faddp s0, v0.2s
; CHECK-NEXT: ret
-;
-; CHECKNOFP16-LABEL: add_HalfS:
-; CHECKNOFP16: // %bb.0:
-; CHECKNOFP16-NEXT: faddp s0, v0.2s
-; CHECKNOFP16-NEXT: ret
%r = call fast float @llvm.vector.reduce.fadd.f32.v2f32(float -0.0, <2 x float> %bin.rdx)
ret float %r
}
define half @add_HalfH(<4 x half> %bin.rdx) {
-; CHECK-LABEL: add_HalfH:
-; CHECK: // %bb.0:
-; CHECK-NEXT: faddp v0.4h, v0.4h, v0.4h
-; CHECK-NEXT: faddp h0, v0.2h
-; CHECK-NEXT: ret
+; FULLFP16-LABEL: add_HalfH:
+; FULLFP16: // %bb.0:
+; FULLFP16-NEXT: faddp v0.4h, v0.4h, v0.4h
+; FULLFP16-NEXT: faddp h0, v0.2h
+; FULLFP16-NEXT: ret
;
; CHECKNOFP16-LABEL: add_HalfH:
; CHECKNOFP16: // %bb.0:
@@ -48,12 +43,12 @@ define half @add_HalfH(<4 x half> %bin.rdx) {
define half @add_H(<8 x half> %bin.rdx) {
-; CHECK-LABEL: add_H:
-; CHECK: // %bb.0:
-; CHECK-NEXT: faddp v0.8h, v0.8h, v0.8h
-; CHECK-NEXT: faddp v0.8h, v0.8h, v0.8h
-; CHECK-NEXT: faddp h0, v0.2h
-; CHECK-NEXT: ret
+; FULLFP16-LABEL: add_H:
+; FULLFP16: // %bb.0:
+; FULLFP16-NEXT: faddp v0.8h, v0.8h, v0.8h
+; FULLFP16-NEXT: faddp v0.8h, v0.8h, v0.8h
+; FULLFP16-NEXT: faddp h0, v0.2h
+; FULLFP16-NEXT: ret
;
; CHECKNOFP16-LABEL: add_H:
; CHECKNOFP16: // %bb.0:
@@ -103,12 +98,6 @@ define float @add_S(<4 x float> %bin.rdx) {
; CHECK-NEXT: faddp v0.4s, v0.4s, v0.4s
; CHECK-NEXT: faddp s0, v0.2s
; CHECK-NEXT: ret
-;
-; CHECKNOFP16-LABEL: add_S:
-; CHECKNOFP16: // %bb.0:
-; CHECKNOFP16-NEXT: faddp v0.4s, v0.4s, v0.4s
-; CHECKNOFP16-NEXT: faddp s0, v0.2s
-; CHECKNOFP16-NEXT: ret
%r = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float -0.0, <4 x float> %bin.rdx)
ret float %r
}
@@ -118,23 +107,18 @@ define double @add_D(<2 x double> %bin.rdx) {
; CHECK: // %bb.0:
; CHECK-NEXT: faddp d0, v0.2d
; CHECK-NEXT: ret
-;
-; CHECKNOFP16-LABEL: add_D:
-; CHECKNOFP16: // %bb.0:
-; CHECKNOFP16-NEXT: faddp d0, v0.2d
-; CHECKNOFP16-NEXT: ret
%r = call fast double @llvm.vector.reduce.fadd.f64.v2f64(double -0.0, <2 x double> %bin.rdx)
ret double %r
}
define half @add_2H(<16 x half> %bin.rdx) {
-; CHECK-LABEL: add_2H:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fadd v0.8h, v0.8h, v1.8h
-; CHECK-NEXT: faddp v0.8h, v0.8h, v0.8h
-; CHECK-NEXT: faddp v0.8h, v0.8h, v0.8h
-; CHECK-NEXT: faddp h0, v0.2h
-; CHECK-NEXT: ret
+; FULLFP16-LABEL: add_2H:
+; FULLFP16: // %bb.0:
+; FULLFP16-NEXT: fadd v0.8h, v0.8h, v1.8h
+; FULLFP16-NEXT: faddp v0.8h, v0.8h, v0.8h
+; FULLFP16-NEXT: faddp v0.8h, v0.8h, v0.8h
+; FULLFP16-NEXT: faddp h0, v0.2h
+; FULLFP16-NEXT: ret
;
; CHECKNOFP16-LABEL: add_2H:
; CHECKNOFP16: // %bb.0:
@@ -224,13 +208,6 @@ define float @add_2S(<8 x float> %bin.rdx) {
; CHECK-NEXT: faddp v0.4s, v0.4s, v0.4s
; CHECK-NEXT: faddp s0, v0.2s
; CHECK-NEXT: ret
-;
-; CHECKNOFP16-LABEL: add_2S:
-; CHECKNOFP16: // %bb.0:
-; CHECKNOFP16-NEXT: fadd v0.4s, v0.4s, v1.4s
-; CHECKNOFP16-NEXT: faddp v0.4s, v0.4s, v0.4s
-; CHECKNOFP16-NEXT: faddp s0, v0.2s
-; CHECKNOFP16-NEXT: ret
%r = call fast float @llvm.vector.reduce.fadd.f32.v8f32(float -0.0, <8 x float> %bin.rdx)
ret float %r
}
@@ -241,12 +218,6 @@ define double @add_2D(<4 x double> %bin.rdx) {
; CHECK-NEXT: fadd v0.2d, v0.2d, v1.2d
; CHECK-NEXT: faddp d0, v0.2d
; CHECK-NEXT: ret
-;
-; CHECKNOFP16-LABEL: add_2D:
-; CHECKNOFP16: // %bb.0:
-; CHECKNOFP16-NEXT: fadd v0.2d, v0.2d, v1.2d
-; CHECKNOFP16-NEXT: faddp d0, v0.2d
-; CHECKNOFP16-NEXT: ret
%r = call fast double @llvm.vector.reduce.fadd.f64.v4f64(double -0.0, <4 x double> %bin.rdx)
ret double %r
}
@@ -261,15 +232,6 @@ define float @add_S_init_42(<4 x float> %bin.rdx) {
; CHECK-NEXT: faddp s0, v0.2s
; CHECK-NEXT: fadd s0, s0, s1
; CHECK-NEXT: ret
-;
-; CHECKNOFP16-LABEL: add_S_init_42:
-; CHECKNOFP16: // %bb.0:
-; CHECKNOFP16-NEXT: faddp v0.4s, v0.4s, v0.4s
-; CHECKNOFP16-NEXT: mov w8, #1109917696
-; CHECKNOFP16-NEXT: fmov s1, w8
-; CHECKNOFP16-NEXT: faddp s0, v0.2s
-; CHECKNOFP16-NEXT: fadd s0, s0, s1
-; CHECKNOFP16-NEXT: ret
%r = call fast float @llvm.vector.reduce.fadd.f32.v4f32(float 42.0, <4 x float> %bin.rdx)
ret float %r
}
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