[PATCH] D120699: [RISCV] Add FMV_W_X and FMV_H_X instrutions to hasAllNBitUsers

[WangLian via Phabricator via llvm-commits]

Jimerlife created this revision.
Jimerlife added reviewers: craig.topper, asb, benshi001.
Jimerlife added a project: LLVM.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Jimerlife requested review of this revision.
Herald added subscribers: llvm-commits, pcwang-thead, eopXD, jacquesguan, MaskRay.

I think fmv.w.x and fmv.h.x also applied to hasAllNBitUsers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120699

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp


Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1850,6 +1850,7 @@
     case RISCV::CTZW:
     case RISCV::CPOPW:
     case RISCV::SLLI_UW:
+    case RISCV::FMV_W_X:
     case RISCV::FCVT_H_W:
     case RISCV::FCVT_H_WU:
     case RISCV::FCVT_S_W:
@@ -1873,6 +1874,7 @@
         return false;
       break;
     case RISCV::SEXT_H:
+    case RISCV::FMV_H_X:
     case RISCV::ZEXT_H_RV32:
     case RISCV::ZEXT_H_RV64:
       if (Bits < 16)


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D120699.411983.patch
Type: text/x-patch
Size: 610 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220301/8c0ba832/attachment.bin>