[PATCH] D120695: [RISCV] Move class RISCVPassConfig declaration to RISCVTargetMachine.h for downstream. NFC
Jim Lin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 28 22:25:13 PST 2022
Jim updated this revision to Diff 411976.
Jim added a comment.
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Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D120695/new/
https://reviews.llvm.org/D120695
Files:
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.h
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -15,7 +15,9 @@
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "RISCVSubtarget.h"
+#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
@@ -47,6 +49,29 @@
virtual bool isNoopAddrSpaceCast(unsigned SrcAS,
unsigned DstAS) const override;
};
+
+class RISCVPassConfig : public TargetPassConfig {
+public:
+ RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
+
+ RISCVTargetMachine &getRISCVTargetMachine() const {
+ return getTM<RISCVTargetMachine>();
+ }
+
+ void addIRPasses() override;
+ bool addInstSelector() override;
+ bool addIRTranslator() override;
+ bool addLegalizeMachineIR() override;
+ bool addRegBankSelect() override;
+ bool addGlobalInstructionSelect() override;
+ void addPreEmitPass() override;
+ void addPreEmitPass2() override;
+ void addPreSched2() override;
+ void addMachineSSAOptimization() override;
+ void addPreRegAlloc() override;
+ void addPostRegAlloc() override;
+};
} // namespace llvm
#endif
Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -22,9 +22,7 @@
#include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
#include "llvm/CodeGen/GlobalISel/Legalizer.h"
#include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
-#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
-#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/LegacyPassManager.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/TargetRegistry.h"
@@ -127,31 +125,6 @@
return true;
}
-namespace {
-class RISCVPassConfig : public TargetPassConfig {
-public:
- RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
- : TargetPassConfig(TM, PM) {}
-
- RISCVTargetMachine &getRISCVTargetMachine() const {
- return getTM<RISCVTargetMachine>();
- }
-
- void addIRPasses() override;
- bool addInstSelector() override;
- bool addIRTranslator() override;
- bool addLegalizeMachineIR() override;
- bool addRegBankSelect() override;
- bool addGlobalInstructionSelect() override;
- void addPreEmitPass() override;
- void addPreEmitPass2() override;
- void addPreSched2() override;
- void addMachineSSAOptimization() override;
- void addPreRegAlloc() override;
- void addPostRegAlloc() override;
-};
-} // namespace
-
TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
return new RISCVPassConfig(*this, PM);
}
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