[llvm] e2c150a - [RISCV][NFC] Move defined non_imm12 to proper place in RISCVInstrInfoZb.td

Lian Wang via llvm-commits llvm-commits at lists.llvm.org
Mon Feb 28 17:47:56 PST 2022


Author: Lian Wang
Date: 2022-03-01T01:45:30Z
New Revision: e2c150ab5278b4ea7497c355f44933f3a59f33c1

URL: https://github.com/llvm/llvm-project/commit/e2c150ab5278b4ea7497c355f44933f3a59f33c1
DIFF: https://github.com/llvm/llvm-project/commit/e2c150ab5278b4ea7497c355f44933f3a59f33c1.diff

LOG: [RISCV][NFC] Move defined non_imm12 to proper place in RISCVInstrInfoZb.td

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D120656

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 2485c744065f7..c588dafcdb7d0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -232,6 +232,12 @@ def SimmShiftRightBy3XForm : SDNodeXForm<imm, [{
                                    N->getValueType(0));
 }]>;
 
+// Pattern to exclude simm12 immediates from matching.
+def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
+  auto *C = dyn_cast<ConstantSDNode>(N);
+  return !C || !isInt<12>(C->getSExtValue());
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
@@ -1042,12 +1048,6 @@ def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV32 GPR:$rs)>;
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
 def : Pat<(i64 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>;
 
-// Pattern to exclude simm12 immediates from matching.
-def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
-  auto *C = dyn_cast<ConstantSDNode>(N);
-  return !C || !isInt<12>(C->getSExtValue());
-}]>;
-
 let Predicates = [HasStdExtZba] in {
 def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), non_imm12:$rs2),
           (SH1ADD GPR:$rs1, GPR:$rs2)>;


        


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