[PATCH] D120686: [RISCV] Don't combine ROTR ((GREV x, 24), 16)->(GREV x, 8) on RV64.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: Chenbing.Zheng, frasercrmck, asb, benshi001, luismarques, jrtc27.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, StephenFan, vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

This miscompile was introduced in D119527 <https://reviews.llvm.org/D119527>.

This was a special pattern for rotate+bswap on RV32. It doesn't
work for RV64 since the rotate needs to be half the bitwidth. The
equivalent pattern for RV64 is ROTR ((GREV x, 56), 32) so match
that instead.

This could be generalized further as noted in the new FIXME.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120686

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbp.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D120686.411895.patch
Type: text/x-patch
Size: 10996 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220228/5ecaa7aa/attachment.bin>