[llvm] e83db8c - [RISCV] Only enable combineROTR_ROTL_RORW_ROLW with Zbp.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-02-28T12:47:36-08:00
New Revision: e83db8c001b81b4d9a44d76b38c5fe22c8d0c5d1

URL: https://github.com/llvm/llvm-project/commit/e83db8c001b81b4d9a44d76b38c5fe22c8d0c5d1
DIFF: https://github.com/llvm/llvm-project/commit/e83db8c001b81b4d9a44d76b38c5fe22c8d0c5d1.diff

LOG: [RISCV] Only enable combineROTR_ROTL_RORW_ROLW with Zbp.

I think the immediate values we check for on the GREV nodes already
protect this, but better to be explicit.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b7e9d0cdff5e7..801d629c4ffbd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1031,8 +1031,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setTargetDAGCombine(ISD::AND);
   setTargetDAGCombine(ISD::OR);
   setTargetDAGCombine(ISD::XOR);
-  setTargetDAGCombine(ISD::ROTL);
-  setTargetDAGCombine(ISD::ROTR);
+  if (Subtarget.hasStdExtZbp()) {
+    setTargetDAGCombine(ISD::ROTL);
+    setTargetDAGCombine(ISD::ROTR);
+  }
   setTargetDAGCombine(ISD::ANY_EXTEND);
   setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
   if (Subtarget.hasStdExtZfh())
@@ -7305,7 +7307,8 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
 // ROTL ((GREV x, 24), 16) -> (GREVI x, 8)
 // RORW ((GREVW x, 24), 16) -> (GREVIW x, 8)
 // ROLW ((GREVW x, 24), 16) -> (GREVIW x, 8)
-static SDValue combineROTR_ROTL_RORW_ROLW(SDNode *N, SelectionDAG &DAG) {
+static SDValue combineROTR_ROTL_RORW_ROLW(SDNode *N, SelectionDAG &DAG,
+                                          const RISCVSubtarget &Subtarget) {
   assert((N->getOpcode() == ISD::ROTR || N->getOpcode() == ISD::ROTL ||
           N->getOpcode() == RISCVISD::RORW ||
           N->getOpcode() == RISCVISD::ROLW) &&
@@ -7314,6 +7317,9 @@ static SDValue combineROTR_ROTL_RORW_ROLW(SDNode *N, SelectionDAG &DAG) {
   SDLoc DL(N);
   unsigned Opc;
 
+  if (!Subtarget.hasStdExtZbp())
+    return SDValue();
+
   if ((N->getOpcode() == ISD::ROTR || N->getOpcode() == ISD::ROTL) &&
       Src.getOpcode() == RISCVISD::GREV)
     Opc = RISCVISD::GREV;
@@ -8081,7 +8087,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
         return SDValue(N, 0);
     }
 
-    return combineROTR_ROTL_RORW_ROLW(N, DAG);
+    return combineROTR_ROTL_RORW_ROLW(N, DAG, Subtarget);
   }
   case RISCVISD::CLZW:
   case RISCVISD::CTZW: {