[PATCH] D120641: [RISCV] Add codegen for vp.fptosi.

[Craig Topper via Phabricator via llvm-commits]

craig.topper requested changes to this revision.
craig.topper added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3684
+  case ISD::VP_FPTOSI:
+    return lowerVPOp(Op, DAG, RISCVISD::FP_TO_SINT_VL);
   }
----------------
This doesn't work if the int and FP types don't have the same element size. FP_TO_SINT_VL does not guarantee this. See the lowering for ISD::FP_TO_SINT which has to handle widening, narrowing, and multi instruction cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120641/new/

https://reviews.llvm.org/D120641