[llvm] b083157 - [RISCV] Don't call combineROTR_ROTL_RORW_ROLW for SLLW/SRLW/SRAW nodes. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-02-28T11:05:10-08:00
New Revision: b083157b7be529cce9ba14c46545c70d6e10882b

URL: https://github.com/llvm/llvm-project/commit/b083157b7be529cce9ba14c46545c70d6e10882b
DIFF: https://github.com/llvm/llvm-project/commit/b083157b7be529cce9ba14c46545c70d6e10882b.diff

LOG: [RISCV] Don't call combineROTR_ROTL_RORW_ROLW for SLLW/SRLW/SRAW nodes. NFC

I think the function does the correct thing internally, but it's
confusing to read.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6261b6a5aee80..b7e9d0cdff5e7 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7306,6 +7306,10 @@ static SDValue transformAddShlImm(SDNode *N, SelectionDAG &DAG,
 // RORW ((GREVW x, 24), 16) -> (GREVIW x, 8)
 // ROLW ((GREVW x, 24), 16) -> (GREVIW x, 8)
 static SDValue combineROTR_ROTL_RORW_ROLW(SDNode *N, SelectionDAG &DAG) {
+  assert((N->getOpcode() == ISD::ROTR || N->getOpcode() == ISD::ROTL ||
+          N->getOpcode() == RISCVISD::RORW ||
+          N->getOpcode() == RISCVISD::ROLW) &&
+         "Unexpected opcode!");
   SDValue Src = N->getOperand(0);
   SDLoc DL(N);
   unsigned Opc;
@@ -8058,19 +8062,27 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
   }
   case RISCVISD::SLLW:
   case RISCVISD::SRAW:
-  case RISCVISD::SRLW:
-  case RISCVISD::ROLW:
-  case RISCVISD::RORW: {
+  case RISCVISD::SRLW: {
     // Only the lower 32 bits of LHS and lower 5 bits of RHS are read.
     if (SimplifyDemandedLowBitsHelper(0, 32) ||
         SimplifyDemandedLowBitsHelper(1, 5))
       return SDValue(N, 0);
 
-    return combineROTR_ROTL_RORW_ROLW(N, DAG);
+    break;
   }
   case ISD::ROTR:
   case ISD::ROTL:
+  case RISCVISD::RORW:
+  case RISCVISD::ROLW: {
+    if (N->getOpcode() == RISCVISD::RORW || N->getOpcode() == RISCVISD::ROLW) {
+      // Only the lower 32 bits of LHS and lower 5 bits of RHS are read.
+      if (SimplifyDemandedLowBitsHelper(0, 32) ||
+          SimplifyDemandedLowBitsHelper(1, 5))
+        return SDValue(N, 0);
+    }
+
     return combineROTR_ROTL_RORW_ROLW(N, DAG);
+  }
   case RISCVISD::CLZW:
   case RISCVISD::CTZW: {
     // Only the lower 32 bits of the first operand are read