[PATCH] D120667: [DAGCombine][RISCV] Fold (bitreverse (srl X, C)) -> (shl (bitreverse X), C) if X is a bswap.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: Chenbing.Zheng, RKSimon, spatel, lebedev.ri, asb, luismarques.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, StephenFan, vkmr, frasercrmck, ecnelises, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

This brings the bswap and bitrevserse together which can enable
more simplifications if the bitreverse needs to be expanded.

This improves the same test cases as D120648 <https://reviews.llvm.org/D120648>, but I think this
improvement is better as it gives a shift pair after the brev8
which could be a zext.h or zext.w if they were enabled in the test.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120667

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/RISCV/bswap-bitreverse.ll


Index: llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
===================================================================
--- llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
+++ llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
@@ -848,19 +848,15 @@
 ;
 ; RV32ZBKB-LABEL: test_bswap_bitreverse_i16:
 ; RV32ZBKB:       # %bb.0:
-; RV32ZBKB-NEXT:    rev8 a0, a0
-; RV32ZBKB-NEXT:    srli a0, a0, 16
-; RV32ZBKB-NEXT:    rev8 a0, a0
 ; RV32ZBKB-NEXT:    brev8 a0, a0
+; RV32ZBKB-NEXT:    slli a0, a0, 16
 ; RV32ZBKB-NEXT:    srli a0, a0, 16
 ; RV32ZBKB-NEXT:    ret
 ;
 ; RV64ZBKB-LABEL: test_bswap_bitreverse_i16:
 ; RV64ZBKB:       # %bb.0:
-; RV64ZBKB-NEXT:    rev8 a0, a0
-; RV64ZBKB-NEXT:    srli a0, a0, 48
-; RV64ZBKB-NEXT:    rev8 a0, a0
 ; RV64ZBKB-NEXT:    brev8 a0, a0
+; RV64ZBKB-NEXT:    slli a0, a0, 48
 ; RV64ZBKB-NEXT:    srli a0, a0, 48
 ; RV64ZBKB-NEXT:    ret
   %tmp = call i16 @llvm.bswap.i16(i16 %a)
@@ -977,10 +973,8 @@
 ;
 ; RV64ZBKB-LABEL: test_bswap_bitreverse_i32:
 ; RV64ZBKB:       # %bb.0:
-; RV64ZBKB-NEXT:    rev8 a0, a0
-; RV64ZBKB-NEXT:    srli a0, a0, 32
-; RV64ZBKB-NEXT:    rev8 a0, a0
 ; RV64ZBKB-NEXT:    brev8 a0, a0
+; RV64ZBKB-NEXT:    slli a0, a0, 32
 ; RV64ZBKB-NEXT:    srli a0, a0, 32
 ; RV64ZBKB-NEXT:    ret
   %tmp = call i32 @llvm.bswap.i32(i32 %a)
@@ -1238,19 +1232,15 @@
 ;
 ; RV32ZBKB-LABEL: test_bitreverse_bswap_i16:
 ; RV32ZBKB:       # %bb.0:
-; RV32ZBKB-NEXT:    rev8 a0, a0
-; RV32ZBKB-NEXT:    srli a0, a0, 16
-; RV32ZBKB-NEXT:    rev8 a0, a0
 ; RV32ZBKB-NEXT:    brev8 a0, a0
+; RV32ZBKB-NEXT:    slli a0, a0, 16
 ; RV32ZBKB-NEXT:    srli a0, a0, 16
 ; RV32ZBKB-NEXT:    ret
 ;
 ; RV64ZBKB-LABEL: test_bitreverse_bswap_i16:
 ; RV64ZBKB:       # %bb.0:
-; RV64ZBKB-NEXT:    rev8 a0, a0
-; RV64ZBKB-NEXT:    srli a0, a0, 48
-; RV64ZBKB-NEXT:    rev8 a0, a0
 ; RV64ZBKB-NEXT:    brev8 a0, a0
+; RV64ZBKB-NEXT:    slli a0, a0, 48
 ; RV64ZBKB-NEXT:    srli a0, a0, 48
 ; RV64ZBKB-NEXT:    ret
   %tmp = call i16 @llvm.bitreverse.i16(i16 %a)
@@ -1367,10 +1357,8 @@
 ;
 ; RV64ZBKB-LABEL: test_bitreverse_bswap_i32:
 ; RV64ZBKB:       # %bb.0:
-; RV64ZBKB-NEXT:    rev8 a0, a0
-; RV64ZBKB-NEXT:    srli a0, a0, 32
-; RV64ZBKB-NEXT:    rev8 a0, a0
 ; RV64ZBKB-NEXT:    brev8 a0, a0
+; RV64ZBKB-NEXT:    slli a0, a0, 32
 ; RV64ZBKB-NEXT:    srli a0, a0, 32
 ; RV64ZBKB-NEXT:    ret
   %tmp = call i32 @llvm.bitreverse.i32(i32 %a)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9693,6 +9693,23 @@
   // fold (bitreverse (bitreverse x)) -> x
   if (N0.getOpcode() == ISD::BITREVERSE)
     return N0.getOperand(0);
+
+  // Canonicalize (bitreverse (srl X, C)) -> (shl (bitreverse X), C) if X is a
+  // bswap.
+  if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
+      isa<ConstantSDNode>(N0.getOperand(1)) &&
+      N0.getOperand(0).getOpcode() == ISD::BSWAP) {
+    auto *N0C1 = cast<ConstantSDNode>(N0.getOperand(1));
+    unsigned OpSizeInBits = VT.getScalarSizeInBits();
+    if (N0C1->getAPIntValue().ult(OpSizeInBits)) {
+      unsigned C1 = N0C1->getZExtValue();
+      SDLoc DL(N);
+      SDValue Rev = DAG.getNode(ISD::BITREVERSE, DL, VT, N0.getOperand(0));
+      return DAG.getNode(ISD::SHL, DL, VT, Rev,
+                         DAG.getConstant(C1, DL, VT));
+    }
+  }
+
   return SDValue();
 }
 


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