[PATCH] D120648: [RISCV] DAGcombine fold (bswap(srl (bswap c), x)) -> (shl c, x)
Chenbing.Zheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 28 05:54:32 PST 2022
Chenbing.Zheng added a comment.
In D120648#3348733 <https://reviews.llvm.org/D120648#3348733>, @RKSimon wrote:
> I think you need to confirm that the shift amount is a multiple of 8 ? https://alive2.llvm.org/ce/z/5DdJRS
Thanks, I agree with you
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