[PATCH] D120648: [RISCV] DAG combine bswap(srl (bswap t), x) to shl t, x

[Chenbing.Zheng via Phabricator via llvm-commits]

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Combine 
t2 = bswap t1;  t3 = srl t2, x;  bswap t3
to shl t1, x.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120648

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/bswap-bitreverse.ll

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