[llvm] 386c5be - [RISCV] Support Sinval extension and hypervisor memory management fence instructions
Eric Tang via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 27 22:08:36 PST 2022
Author: eric.tang
Date: 2022-02-28T14:02:43+08:00
New Revision: 386c5be92a861f6aae95667e9ede2c573af84089
URL: https://github.com/llvm/llvm-project/commit/386c5be92a861f6aae95667e9ede2c573af84089
DIFF: https://github.com/llvm/llvm-project/commit/386c5be92a861f6aae95667e9ede2c573af84089.diff
LOG: [RISCV] Support Sinval extension and hypervisor memory management fence instructions
According to Privileged spec version-20211203
Add Supervisor Memory-Management Instructions:
- SINVAL.VMA, SFENCE.W.INVAL, SFENCE.INVAL.IR
Add Hypervisor Memory-Management Instructions:
- HFENCE.VVMA, HFENCE.GVMA, HINVAL.VVMA, HINVAL.GVMA
Signed-off-by: eric.tang <eric.tang at starfivetech.com>
Differential Revision: https://reviews.llvm.org/D117654
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/MC/RISCV/priv-invalid.s
llvm/test/MC/RISCV/priv-valid.s
llvm/test/MC/RISCV/rvi-aliases-valid.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index fb1ec3f3bfc42..30627ebc8179e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -512,6 +512,13 @@ class Priv<string opcodestr, bits<7> funct7>
: RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2),
opcodestr, "">;
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+class Priv_rr<string opcodestr, bits<7> funct7>
+ : RVInstR<funct7, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2),
+ opcodestr, "$rs1, $rs2"> {
+ let rd = 0;
+}
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -697,13 +704,25 @@ def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {
let rs2 = 0b00101;
}
-let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
-def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
- (ins GPR:$rs1, GPR:$rs2),
- "sfence.vma", "$rs1, $rs2">, Sched<[]> {
+def SFENCE_W_INVAL : Priv<"sfence.w.inval", 0b0001100>, Sched<[]> {
let rd = 0;
+ let rs1 = 0;
+ let rs2 = 0;
}
+def SFENCE_INVAL_IR : Priv<"sfence.inval.ir", 0b0001100>, Sched<[]> {
+ let rd = 0;
+ let rs1 = 0;
+ let rs2 = 0b00001;
+}
+
+def SFENCE_VMA : Priv_rr<"sfence.vma", 0b0001001>, Sched<[]>;
+def SINVAL_VMA : Priv_rr<"sinval.vma", 0b0001011>, Sched<[]>;
+def HFENCE_VVMA : Priv_rr<"hfence.vvma", 0b0010001>, Sched<[]>;
+def HFENCE_GVMA : Priv_rr<"hfence.gvma", 0b0110001>, Sched<[]>;
+def HINVAL_VVMA : Priv_rr<"hinval.vvma", 0b0010011>, Sched<[]>;
+def HINVAL_GVMA : Priv_rr<"hinval.gvma", 0b0110011>, Sched<[]>;
+
//===----------------------------------------------------------------------===//
// Debug instructions
//===----------------------------------------------------------------------===//
@@ -847,6 +866,9 @@ def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5
def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>;
def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
+def : InstAlias<"hfence.gvma", (HFENCE_GVMA X0, X0)>;
+def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs, X0)>;
+
let EmitPriority = 0 in {
def : InstAlias<"lb $rd, (${rs1})",
(LB GPR:$rd, GPR:$rs1, 0)>;
diff --git a/llvm/test/MC/RISCV/priv-invalid.s b/llvm/test/MC/RISCV/priv-invalid.s
index 8f421e471f934..f7c1c2c96f26a 100644
--- a/llvm/test/MC/RISCV/priv-invalid.s
+++ b/llvm/test/MC/RISCV/priv-invalid.s
@@ -5,3 +5,27 @@ mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sinval.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction
+
+sinval.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sfence.w.inval 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
+
+sfence.inval.ir 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hfence.gvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hinval.vvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hinval.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+hinval.gvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+hinval.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s
index 4c79dc41a46de..9e2f87ad4f7e1 100644
--- a/llvm/test/MC/RISCV/priv-valid.s
+++ b/llvm/test/MC/RISCV/priv-valid.s
@@ -32,3 +32,51 @@ sfence.vma zero, zero
# CHECK-INST: sfence.vma a0, a1
# CHECK: encoding: [0x73,0x00,0xb5,0x12]
sfence.vma a0, a1
+
+# CHECK-INST: sinval.vma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x16]
+sinval.vma zero, zero
+
+# CHECK-INST: sinval.vma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x16]
+sinval.vma a0, a1
+
+# CHECK-INST: sfence.w.inval
+# CHECK: encoding: [0x73,0x00,0x00,0x18]
+sfence.w.inval
+
+# CHECK-INST: sfence.inval.ir
+# CHECK: encoding: [0x73,0x00,0x10,0x18]
+sfence.inval.ir
+
+# CHECK-INST: hfence.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x22]
+hfence.vvma zero, zero
+
+# CHECK-INST: hfence.vvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x22]
+hfence.vvma a0, a1
+
+# CHECK-INST: hfence.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x62]
+hfence.gvma zero, zero
+
+# CHECK-INST: hfence.gvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x62]
+hfence.gvma a0, a1
+
+# CHECK-INST: hinval.vvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x26]
+hinval.vvma zero, zero
+
+# CHECK-INST: hinval.vvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x26]
+hinval.vvma a0, a1
+
+# CHECK-INST: hinval.gvma zero, zero
+# CHECK: encoding: [0x73,0x00,0x00,0x66]
+hinval.gvma zero, zero
+
+# CHECK-INST: hinval.gvma a0, a1
+# CHECK: encoding: [0x73,0x00,0xb5,0x66]
+hinval.gvma a0, a1
diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
index 8b166d48992ee..3057e6cfde1d3 100644
--- a/llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -256,6 +256,12 @@ sfence.vma
# CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero
# CHECK-S-OBJ: sfence.vma a0
sfence.vma a0
+# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero
+# CHECK-S-OBJ: hfence.gvma
+hfence.gvma
+# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero
+# CHECK-S-OBJ: hfence.gvma a0
+hfence.gvma a0
# The following aliases are accepted as input but the canonical form
# of the instruction will always be printed.
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