[llvm] 7f811ce - [RISCV] Optimize (sext.w, srli) to sraiw with Zba.
Chenbing Zheng via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 27 18:34:54 PST 2022
Author: Chenbing Zheng
Date: 2022-02-28T10:34:35+08:00
New Revision: 7f811ce12744db67e9d6450541c6bd313e06db59
URL: https://github.com/llvm/llvm-project/commit/7f811ce12744db67e9d6450541c6bd313e06db59
DIFF: https://github.com/llvm/llvm-project/commit/7f811ce12744db67e9d6450541c6bd313e06db59.diff
LOG: [RISCV] Optimize (sext.w, srli) to sraiw with Zba.
In this patch, we add a more narrower exclusion for
zeroext (srl x) -> srli (slli x), so that it provides an opportunity
for the selection of sraiw.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D120467
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 88eeca01d9ac1..06e32eb2827aa 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -772,7 +772,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
}
// (srli (slli x, c3-c2), c3).
- if (OneUseOrZExtW && !IsANDI) {
+ // Skip it in order to select sraiw.
+ bool Skip = Subtarget->hasStdExtZba() && C3 == 32 &&
+ X.getOpcode() == ISD::SIGN_EXTEND_INREG;
+ if (OneUseOrZExtW && !IsANDI && !Skip) {
SDNode *SLLI = CurDAG->getMachineNode(
RISCV::SLLI, DL, XLenVT, X,
CurDAG->getTargetConstant(C3 - C2, DL, XLenVT));
diff --git a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
index 777c814813cff..22791dd99465e 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
@@ -1935,14 +1935,19 @@ define signext i32 @sext_sraiw_zext(i32 zeroext %a) nounwind {
ret i32 %1
}
-; TODO: The sext.w+srli can be replaced with sraiw with Zba.
define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
-; RV64-LABEL: zext_sraiw_aext:
-; RV64: # %bb.0:
-; RV64-NEXT: sext.w a0, a0
-; RV64-NEXT: slli a0, a0, 25
-; RV64-NEXT: srli a0, a0, 32
-; RV64-NEXT: ret
+; RV64I-LABEL: zext_sraiw_aext:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: slli a0, a0, 25
+; RV64I-NEXT: srli a0, a0, 32
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraiw_aext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraiw a0, a0, 7
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, 7
ret i32 %1
}
@@ -1957,14 +1962,19 @@ define zeroext i32 @zext_sraiw_sext(i32 signext %a) nounwind {
ret i32 %1
}
-; TODO: The sext.w+srli can be replaced with sraiw with Zba.
define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
-; RV64-LABEL: zext_sraiw_zext:
-; RV64: # %bb.0:
-; RV64-NEXT: sext.w a0, a0
-; RV64-NEXT: slli a0, a0, 23
-; RV64-NEXT: srli a0, a0, 32
-; RV64-NEXT: ret
+; RV64I-LABEL: zext_sraiw_zext:
+; RV64I: # %bb.0:
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: slli a0, a0, 23
+; RV64I-NEXT: srli a0, a0, 32
+; RV64I-NEXT: ret
+;
+; RV64ZBA-LABEL: zext_sraiw_zext:
+; RV64ZBA: # %bb.0:
+; RV64ZBA-NEXT: sraiw a0, a0, 9
+; RV64ZBA-NEXT: zext.w a0, a0
+; RV64ZBA-NEXT: ret
%1 = ashr i32 %a, 9
ret i32 %1
}
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