[PATCH] D111530: [TargetLowering] Optimize expanded SRL/SHL fed into SETCC ne/eq 0

Sun Feb 27 08:44:11 PST 2022

spatel added a comment.

In D111530#3332382 <https://reviews.llvm.org/D111530#3332382>, @fzhinkin wrote:

> Transformation from this change is not only about shifts recombination but (and mostly) about removal of shifts that will rotate bits of a value compared with zero. In that particular case such shifts could be safely eliminated, but in any other case it's not possible as it will change the result.

Now that we're reducing the pattern more with:
acb96ffd149db447 <https://reviews.llvm.org/rGacb96ffd149db447b78d3ab33fbc9f93ce781c46>
...I see what you mean. We were missing a transform that already exists in IR:
69684b84c61c <https://reviews.llvm.org/rG69684b84c61c39f643d09d617c5af3ba5f7a30c4>

We still need 1-2 other patches to fix the motivating example, but I think we can get there with some small peepholes.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D111530/new/

https://reviews.llvm.org/D111530