[PATCH] D120606: [WIP][M68k][Disassembler] Adopt the new variable length infrastructure in disassembler

[Sheng via Phabricator via llvm-commits]

0x59616e added a comment.

FYI, here are the instructions that have decoding conflict:

OR16dd / OR16dr
OR32dd/ OR32dr
SUB16dd / SUB16dr
SUB32dd / SUB32dr
AND16dd / AND16dr
AND32dd / AND32dr
ADD16dd / ADD16dr
ADD32dd / ADD32dr

I have two ideas:

- Decode these instruction manually. Add a flag to suppress the "decode conflict" message in TableGen
- Refactor these instruction. For example, can ADD32dd be removed and only use ADD32dr ?


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  https://reviews.llvm.org/D120606/new/

https://reviews.llvm.org/D120606