[PATCH] D120192: [DAG] Attempt to fold bswap(shl(x,c)) -> zext(bswap(trunc(shl(x,c-bw/2))))

[Nathan Chancellor via Phabricator via llvm-commits]

nathanchance added a comment.

This patch causes a failed assertion when building the arm64 Linux kernel.

A reduced C reproducer:

  struct mlx5_ifc_cmd_hca_cap_bits {
    char gid_table_size[16]
  };
  enum { MLX5_CAP_GENERAL, MLX5_CAP_NUM };
  struct mlx5_hca_cap {
    int cur[0]
  };
  struct mlx5_core_dev {
    struct {
      struct mlx5_hca_cap *hca[MLX5_CAP_NUM]
    } caps
  };
  short mlx5_query_hca_port_props_1;
  mlx5_query_hca_port___trans_tmp_1;
  mlx5_query_hca_port() {
    struct mlx5_core_dev *dev = to_mdev();
    int rep = mlx5_query_hca_port___trans_tmp_1 = __builtin_constant_p(0);
    gid_tbl_len(
        (mlx5_query_hca_port___trans_tmp_1
             ? *dev->caps.hca[MLX5_CAP_GENERAL]->cur << 24 |
                   (*dev->caps.hca[MLX5_CAP_GENERAL]->cur & 16711680) >> 8 |
                   (*dev->caps.hca[MLX5_CAP_GENERAL]->cur & 4278190080) >> 24
             : 0) &
        (1 << sizeof((struct mlx5_ifc_cmd_hca_cap_bits *)0)->gid_table_size) - 1);
    mlx5_query_hca_port_props_1 = rep;
  }



  $ clang --target=aarch64-linux-gnu -O2 -c -o /dev/null main.i
  ...
  clang: /home/nathan/cbl/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:979: void (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode *): Assertion `(TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == TargetLowering::TypeLegal || Op.getOpcode() == ISD::TargetConstant || Op.getOpcode() == ISD::Register) && "Unexpected illegal type!"' failed.
  PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace, preprocessed source, and associated run script.
  Stack dump:
  0.      Program arguments: clang --target=aarch64-linux-gnu -O2 -c -o /dev/null main.i
  1.      <eof> parser at end of file
  2.      Code generation
  3.      Running pass 'Function Pass Manager' on module 'main.i'.
  4.      Running pass 'AArch64 Instruction Selection' on function '@mlx5_query_hca_port'
  ...

A reduced LLVM IR reproducer:

  target triple = "aarch64-unknown-linux-gnu"
  
  @mlx5_query_hca_port_props_1 = external global i16
  
  define i32 @mlx5_query_hca_port(i16* %mlx5_query_hca_port_props_1) {
  entry:
    %0 = load i32, i32* null, align 4
    %1 = and i32 %0, -65536
    %2 = tail call i32 @llvm.bswap.i32(i32 %1)
    %and16 = zext i32 %2 to i64
    %call17 = tail call i32 bitcast (i32 (...)* @gid_tbl_len to i32 (i64)*)(i64 %and16)
    store i16 0, i16* %mlx5_query_hca_port_props_1, align 4
    ret i32 0
  }
  
  declare i32 @to_mdev(...)
  
  declare i32 @gid_tbl_len(...)
  
  ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
  declare i32 @llvm.bswap.i32(i32) #0
  
  attributes #0 = { nofree nosync nounwind readnone speculatable willreturn }



  $ llc reduced.ll
  llc: /home/nathan/cbl/src/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:979: void (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode *): Assertion `(TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == TargetLowering::TypeLegal || Op.getOpcode() == ISD::TargetConstant || Op.getOpcode() == ISD::Register) && "Unexpected illegal type!"' failed.
  PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace.
  Stack dump:
  0.      Program arguments: llc reduced.ll
  1.      Running pass 'Function Pass Manager' on module 'reduced.ll'.
  2.      Running pass 'AArch64 Instruction Selection' on function '@mlx5_query_hca_port'
  ...


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D120192/new/

https://reviews.llvm.org/D120192