[PATCH] D120548: [AArch64] Try to convert signed to unsigned pred to re-use zext.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
fhahn added reviewers: t.p.northover, ab, dmgreen, paquette.
Herald added subscribers: hiraditya, kristof.beyls.
fhahn requested review of this revision.
Herald added a project: LLVM.

Building on D120481 <https://reviews.llvm.org/D120481>, try to convert a signed predicate to unsigned to
re-use existing zext.

The following conversion is supported: %a >s -1 -> zext(%a) <u 128.
https://alive2.llvm.org/ce/z/RVnadn

Depends on D120481 <https://reviews.llvm.org/D120481>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120548

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/vselect-ext.ll


Index: llvm/test/CodeGen/AArch64/vselect-ext.ll
===================================================================
--- llvm/test/CodeGen/AArch64/vselect-ext.ll
+++ llvm/test/CodeGen/AArch64/vselect-ext.ll
@@ -166,24 +166,21 @@
 define <16 x i32> @same_zext_used_in_cmp_signed_pred_and_select_can_convert_to_unsigned_pred(<16 x i8> %a) {
 ; CHECK-LABEL: same_zext_used_in_cmp_signed_pred_and_select_can_convert_to_unsigned_pred:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    movi.2d v1, #0xffffffffffffffff
-; CHECK-NEXT:    ushll.8h v2, v0, #0
-; CHECK-NEXT:    ushll2.8h v3, v0, #0
-; CHECK-NEXT:    ushll.4s v4, v2, #0
-; CHECK-NEXT:    cmgt.16b v0, v0, v1
-; CHECK-NEXT:    ushll.4s v5, v3, #0
-; CHECK-NEXT:    ushll2.4s v1, v3, #0
-; CHECK-NEXT:    sshll.8h v3, v0, #0
-; CHECK-NEXT:    sshll2.8h v0, v0, #0
-; CHECK-NEXT:    ushll2.4s v2, v2, #0
-; CHECK-NEXT:    sshll.4s v6, v3, #0
-; CHECK-NEXT:    sshll.4s v7, v0, #0
-; CHECK-NEXT:    sshll2.4s v0, v0, #0
-; CHECK-NEXT:    sshll2.4s v16, v3, #0
-; CHECK-NEXT:    and.16b v3, v1, v0
-; CHECK-NEXT:    and.16b v1, v2, v16
-; CHECK-NEXT:    and.16b v2, v5, v7
-; CHECK-NEXT:    and.16b v0, v4, v6
+; CHECK-NEXT:    movi.2d v1, #0x0000ff000000ff
+; CHECK-NEXT:    ushll2.8h v2, v0, #0
+; CHECK-NEXT:    ushll.8h v0, v0, #0
+; CHECK-NEXT:    ushll2.4s v3, v2, #0
+; CHECK-NEXT:    ushll2.4s v4, v0, #0
+; CHECK-NEXT:    ushll.4s v0, v0, #0
+; CHECK-NEXT:    ushll.4s v2, v2, #0
+; CHECK-NEXT:    cmhi.4s v5, v1, v0
+; CHECK-NEXT:    cmhi.4s v6, v1, v2
+; CHECK-NEXT:    cmhi.4s v7, v1, v3
+; CHECK-NEXT:    cmhi.4s v1, v1, v4
+; CHECK-NEXT:    and.16b v3, v3, v7
+; CHECK-NEXT:    and.16b v1, v4, v1
+; CHECK-NEXT:    and.16b v2, v2, v6
+; CHECK-NEXT:    and.16b v0, v0, v5
 ; CHECK-NEXT:    ret
 entry:
   %ext = zext <16 x i8> %a to <16 x i32>
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -17065,8 +17065,8 @@
       }))
     return SDValue();
 
-  APInt V;
-  if (!ISD::isConstantSplatVector(Op->getOperand(1).getNode(), V))
+  APInt SplatVal;
+  if (!ISD::isConstantSplatVector(Op->getOperand(1).getNode(), SplatVal))
     return SDValue();
 
   SDLoc DL(Op);
@@ -17082,14 +17082,25 @@
   if (Op0SExt && isSignedIntSetCC(CC)) {
     Op0ExtV = SDValue(Op0SExt, 0);
     Op1ExtV = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::v16i32, Op->getOperand(1));
-  } else if (Op0ZExt && isUnsignedIntSetCC(CC)) {
+  } else if (Op0ZExt) {
     Op0ExtV = SDValue(Op0ZExt, 0);
-    Op1ExtV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v16i32, Op->getOperand(1));
-  } else
+    // Try to convert signed to unsigned predicate, so zext can be used: %a >s
+    // -1 -> zext(%a) <u 128.
+    if (CC == ISD::SETGT && SplatVal.isAllOnes()) {
+      CC = ISD::SETULT;
+      Op1ExtV = DAG.getSplatBuildVector(MVT::v16i32, DL,
+                                        DAG.getConstant(128, DL, MVT::i32));
+    }
+    if (isUnsignedIntSetCC(CC))
+      Op1ExtV =
+          DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v16i32, Op->getOperand(1));
+  }
+
+  if (!Op0ExtV || !Op1ExtV)
     return SDValue();
 
   return DAG.getNode(ISD::SETCC, DL, MVT::v16i1, Op0ExtV, Op1ExtV,
-                     Op->getOperand(2));
+                     DAG.getCondCode(CC));
 }
 
 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {


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