[PATCH] D120467: [RISCV] Optimize (sext.w, srli) to sraiw with Zba.

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng updated this revision to Diff 411291.
Chenbing.Zheng added a comment.

Address comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120467/new/

https://reviews.llvm.org/D120467

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll


Index: llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
+++ llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
@@ -1935,14 +1935,19 @@
   ret i32 %1
 }
 
-; TODO: The sext.w+srli can be replaced with sraiw with Zba.
 define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
-; RV64-LABEL: zext_sraiw_aext:
-; RV64:       # %bb.0:
-; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    slli a0, a0, 25
-; RV64-NEXT:    srli a0, a0, 32
-; RV64-NEXT:    ret
+; RV64I-LABEL: zext_sraiw_aext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    slli a0, a0, 25
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: zext_sraiw_aext:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sraiw a0, a0, 7
+; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    ret
   %1 = ashr i32 %a, 7
   ret i32 %1
 }
@@ -1957,14 +1962,19 @@
   ret i32 %1
 }
 
-; TODO: The sext.w+srli can be replaced with sraiw with Zba.
 define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
-; RV64-LABEL: zext_sraiw_zext:
-; RV64:       # %bb.0:
-; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    slli a0, a0, 23
-; RV64-NEXT:    srli a0, a0, 32
-; RV64-NEXT:    ret
+; RV64I-LABEL: zext_sraiw_zext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    slli a0, a0, 23
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: zext_sraiw_zext:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sraiw a0, a0, 9
+; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    ret
   %1 = ashr i32 %a, 9
   ret i32 %1
 }
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -769,7 +769,10 @@
         }
 
         // (srli (slli x, c3-c2), c3).
-        if (OneUseOrZExtW && !IsANDI) {
+        // Skip it in order to select sraiw.
+        bool Skip = Subtarget->hasStdExtZba() && C3 == 32 &&
+                    X.getOpcode() == ISD::SIGN_EXTEND_INREG;
+        if (OneUseOrZExtW && !IsANDI && !Skip) {
           SDNode *SLLI = CurDAG->getMachineNode(
               RISCV::SLLI, DL, XLenVT, X,
               CurDAG->getTargetConstant(C3 - C2, DL, XLenVT));


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