[llvm] f37d21e - [RISCV] Add schedule class for Zbt extension

[Lian Wang via llvm-commits]

Author: lian wang
Date: 2022-02-25T01:57:20Z
New Revision: f37d21ed20fb069b8706b9a4afbac7d373ecb18b

URL: https://github.com/llvm/llvm-project/commit/f37d21ed20fb069b8706b9a4afbac7d373ecb18b
DIFF: https://github.com/llvm/llvm-project/commit/f37d21ed20fb069b8706b9a4afbac7d373ecb18b.diff

LOG: [RISCV] Add schedule class for Zbt extension

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D119808

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/lib/Target/RISCV/RISCVSchedRocket.td
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    llvm/lib/Target/RISCV/RISCVScheduleB.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 3b2e87802446d..2485c744065f7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -429,24 +429,28 @@ def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;
 
 let Predicates = [HasStdExtZbt] in {
 def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">,
-           Sched<[]>;
+           Sched<[WriteCMix, ReadCMix, ReadCMix, ReadCMix]>;
 def CMOV : RVBTernaryR<0b11, 0b101, OPC_OP, "cmov", "$rd, $rs2, $rs1, $rs3">,
-           Sched<[]>;
+           Sched<[WriteCMov, ReadCMov, ReadCMov, ReadCMov]>;
 def FSL  : RVBTernaryR<0b10, 0b001, OPC_OP, "fsl", "$rd, $rs1, $rs3, $rs2">,
-           Sched<[]>;
+           Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>;
 def FSR  : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
-           Sched<[]>;
+           Sched<[WriteFSReg, ReadFSReg, ReadFSReg, ReadFSReg]>;
 def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri",
-                          "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
+                          "$rd, $rs1, $rs3, $shamt">,
+           Sched<[WriteFSRImm, ReadFSRImm, ReadFSRImm]>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbt, IsRV64] in {
 def FSLW  : RVBTernaryR<0b10, 0b001, OPC_OP_32,
-                        "fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
+                        "fslw", "$rd, $rs1, $rs3, $rs2">,
+            Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>;
 def FSRW  : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",
-                        "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
+                        "$rd, $rs1, $rs3, $rs2">,
+            Sched<[WriteFSReg32, ReadFSReg32, ReadFSReg32, ReadFSReg32]>;
 def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32,
-                           "fsriw", "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
+                           "fsriw", "$rd, $rs1, $rs3, $shamt">,
+            Sched<[WriteFSRImm32, ReadFSRImm32, ReadFSRImm32]>;
 } // Predicates = [HasStdExtZbt, IsRV64]
 
 let Predicates = [HasStdExtZbb] in {

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 9f6501c017629..ae36c40bc7ac2 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -245,5 +245,6 @@ defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbe;
 defm : UnsupportedSchedZbf;
 defm : UnsupportedSchedZbm;
+defm : UnsupportedSchedZbt;
 defm : UnsupportedSchedZfh;
 }

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 26b7e08f1426a..ccb62091443bc 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -232,5 +232,6 @@ defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbe;
 defm : UnsupportedSchedZbf;
 defm : UnsupportedSchedZbm;
+defm : UnsupportedSchedZbt;
 defm : UnsupportedSchedZfh;
 }

diff  --git a/llvm/lib/Target/RISCV/RISCVScheduleB.td b/llvm/lib/Target/RISCV/RISCVScheduleB.td
index 2a7d244e4fb73..097dce5e4f47a 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleB.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleB.td
@@ -46,6 +46,14 @@ def WriteBFP32       : SchedWrite; // BFPW
 // Zbm extension
 def WriteBMatrix     : SchedWrite; // bmator/bmatxor/bmatflip
 
+// Zbt extension
+def WriteCMix        : SchedWrite; // cmix
+def WriteCMov        : SchedWrite; // cmov
+def WriteFSReg       : SchedWrite; // fsl/fsr
+def WriteFSRImm      : SchedWrite; // fsri
+def WriteFSReg32     : SchedWrite; // fslw/fsrw
+def WriteFSRImm32    : SchedWrite; // fsriw
+
 /// Define scheduler resources associated with use operands.
 
 // Zba extension
@@ -86,6 +94,14 @@ def ReadBFP32       : SchedRead; // BFPW
 // Zbm extension
 def ReadBMatrix     : SchedRead; // bmator/bmatxor/bmatflip
 
+// Zbt extension
+def ReadCMix        : SchedRead; // cmix
+def ReadCMov        : SchedRead; // cmov
+def ReadFSReg       : SchedRead; // fsl/fsr
+def ReadFSRImm      : SchedRead; // fsri
+def ReadFSReg32     : SchedRead; // fslw/fsrw
+def ReadFSRImm32    : SchedRead; // fsriw
+
 /// Define default scheduler resources for B.
 
 multiclass UnsupportedSchedZba {
@@ -177,3 +193,21 @@ def : WriteRes<WriteBMatrix, []>;
 def : ReadAdvance<ReadBMatrix, 0>;
 }
 }
+
+multiclass UnsupportedSchedZbt {
+let Unsupported = true in {
+def : WriteRes<WriteCMix, []>;
+def : WriteRes<WriteCMov, []>;
+def : WriteRes<WriteFSReg, []>;
+def : WriteRes<WriteFSRImm, []>;
+def : WriteRes<WriteFSReg32, []>;
+def : WriteRes<WriteFSRImm32, []>;
+
+def : ReadAdvance<ReadCMix, 0>;
+def : ReadAdvance<ReadCMov, 0>;
+def : ReadAdvance<ReadFSReg, 0>;
+def : ReadAdvance<ReadFSRImm, 0>;
+def : ReadAdvance<ReadFSReg32, 0>;
+def : ReadAdvance<ReadFSRImm32, 0>;
+}
+}