[PATCH] D120516: [SDAG] fold bitwise logic with shifted operands

[Sanjay Patel via Phabricator via llvm-commits]

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LOGIC (LOGIC (SH X0, Y), Z), (SH X1, Y) --> LOGIC (SH (LOGIC X0, X1), Y), Z

https://alive2.llvm.org/ce/z/QmR9rR

This is effectively a reassociation + distribution fold. The common shift operation is moved after a bitwise logic op on 2 input operands. 
We get simpler cases of these patterns in IR, but I suspect we would miss all of these exact tests in IR too.

This is a partial implementation of a transform suggested in D111530 <https://reviews.llvm.org/D111530> (only handles 'or' bitwise logic as a first step - need to stamp out more tests for other opcodes).
Several of the same tests added for D111530 <https://reviews.llvm.org/D111530> are altered here (but not fully optimized). I'm not sure yet if this would help/hinder that patch, but this should be an improvement for all tests since it removes a shift operation.


https://reviews.llvm.org/D120516

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/icmp-shift-opt.ll
  llvm/test/CodeGen/AArch64/logic-shift.ll
  llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
  llvm/test/CodeGen/ARM/icmp-shift-opt.ll
  llvm/test/CodeGen/X86/icmp-shift-opt.ll
  llvm/test/CodeGen/X86/logic-shift.ll

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