[PATCH] D120462: [AArch64InstrInfo.td] - Lowering fix for cttz intrinsic

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:2053
+          (ANDWri (CLZWr (RBITWr GPR32:$Rn)), (i32 4))>;
 def : Pat<(cttz GPR64:$Rn),
+          (ANDXri (CLZXr (RBITXr GPR64:$Rn)), (i64 5))>;
----------------
This doesn't make sense to me. If you have a plain cttz operation you don't need an AND.

I thought the problem was that you have (select (seteq X, 0), 0, (cttz X)) and you need to turn the select and setcc in to an AND. That needs to be done as a DAGCombine.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120462/new/

https://reviews.llvm.org/D120462