[llvm] 2aa1c6f - [RISCV] Add Zbb RUN lines to neg-abs.ll.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-02-24T10:21:10-08:00
New Revision: 2aa1c6fca12c40f90cd73b84cf48afbebf210798

URL: https://github.com/llvm/llvm-project/commit/2aa1c6fca12c40f90cd73b84cf48afbebf210798
DIFF: https://github.com/llvm/llvm-project/commit/2aa1c6fca12c40f90cd73b84cf48afbebf210798.diff

LOG: [RISCV] Add Zbb RUN lines to neg-abs.ll.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/neg-abs.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/neg-abs.ll b/llvm/test/CodeGen/RISCV/neg-abs.ll
index f2e75792a9170..77d2e3231aadf 100644
--- a/llvm/test/CodeGen/RISCV/neg-abs.ll
+++ b/llvm/test/CodeGen/RISCV/neg-abs.ll
@@ -1,10 +1,14 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV32I
+; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV32ZBB
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV32IBT
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV64I
+; RUN: llc -mtriple=riscv64 -mattr=+zbb -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64ZBB
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV64IBT
 
@@ -19,6 +23,12 @@ define i32 @neg_abs32(i32 %x) {
 ; RV32I-NEXT:    sub a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
+; RV32ZBB-LABEL: neg_abs32:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    neg a1, a0
+; RV32ZBB-NEXT:    min a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
 ; RV32IBT-LABEL: neg_abs32:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    srai a1, a0, 31
@@ -33,6 +43,13 @@ define i32 @neg_abs32(i32 %x) {
 ; RV64I-NEXT:    subw a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
+; RV64ZBB-LABEL: neg_abs32:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    sraiw a1, a0, 31
+; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    subw a0, a1, a0
+; RV64ZBB-NEXT:    ret
+;
 ; RV64IBT-LABEL: neg_abs32:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    sraiw a1, a0, 31
@@ -52,6 +69,12 @@ define i32 @select_neg_abs32(i32 %x) {
 ; RV32I-NEXT:    sub a0, a1, a0
 ; RV32I-NEXT:    ret
 ;
+; RV32ZBB-LABEL: select_neg_abs32:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    neg a1, a0
+; RV32ZBB-NEXT:    min a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
 ; RV32IBT-LABEL: select_neg_abs32:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    srai a1, a0, 31
@@ -66,6 +89,13 @@ define i32 @select_neg_abs32(i32 %x) {
 ; RV64I-NEXT:    subw a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
+; RV64ZBB-LABEL: select_neg_abs32:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    sraiw a1, a0, 31
+; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    subw a0, a1, a0
+; RV64ZBB-NEXT:    ret
+;
 ; RV64IBT-LABEL: select_neg_abs32:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    sraiw a1, a0, 31
@@ -90,6 +120,17 @@ define i64 @neg_abs64(i64 %x) {
 ; RV32I-NEXT:    sub a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
+; RV32ZBB-LABEL: neg_abs64:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    srai a2, a1, 31
+; RV32ZBB-NEXT:    xor a0, a0, a2
+; RV32ZBB-NEXT:    sltu a3, a2, a0
+; RV32ZBB-NEXT:    xor a1, a1, a2
+; RV32ZBB-NEXT:    sub a1, a2, a1
+; RV32ZBB-NEXT:    sub a1, a1, a3
+; RV32ZBB-NEXT:    sub a0, a2, a0
+; RV32ZBB-NEXT:    ret
+;
 ; RV32IBT-LABEL: neg_abs64:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    srai a2, a1, 31
@@ -108,6 +149,12 @@ define i64 @neg_abs64(i64 %x) {
 ; RV64I-NEXT:    sub a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
+; RV64ZBB-LABEL: neg_abs64:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    neg a1, a0
+; RV64ZBB-NEXT:    min a0, a0, a1
+; RV64ZBB-NEXT:    ret
+;
 ; RV64IBT-LABEL: neg_abs64:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    srai a1, a0, 63
@@ -131,6 +178,17 @@ define i64 @select_neg_abs64(i64 %x) {
 ; RV32I-NEXT:    sub a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
+; RV32ZBB-LABEL: select_neg_abs64:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    srai a2, a1, 31
+; RV32ZBB-NEXT:    xor a0, a0, a2
+; RV32ZBB-NEXT:    sltu a3, a2, a0
+; RV32ZBB-NEXT:    xor a1, a1, a2
+; RV32ZBB-NEXT:    sub a1, a2, a1
+; RV32ZBB-NEXT:    sub a1, a1, a3
+; RV32ZBB-NEXT:    sub a0, a2, a0
+; RV32ZBB-NEXT:    ret
+;
 ; RV32IBT-LABEL: select_neg_abs64:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    srai a2, a1, 31
@@ -149,6 +207,12 @@ define i64 @select_neg_abs64(i64 %x) {
 ; RV64I-NEXT:    sub a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
+; RV64ZBB-LABEL: select_neg_abs64:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    neg a1, a0
+; RV64ZBB-NEXT:    min a0, a0, a1
+; RV64ZBB-NEXT:    ret
+;
 ; RV64IBT-LABEL: select_neg_abs64:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    srai a1, a0, 63