[llvm] a975ca9 - [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 24 09:23:09 PST 2022
Author: Craig Topper
Date: 2022-02-24T09:19:01-08:00
New Revision: a975ca97c32f6a696c504a2341d856161663329d
URL: https://github.com/llvm/llvm-project/commit/a975ca97c32f6a696c504a2341d856161663329d
DIFF: https://github.com/llvm/llvm-project/commit/a975ca97c32f6a696c504a2341d856161663329d.diff
LOG: [RISCV] Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X).
Add a new ISD opcode to represent the sign extending behavior of
vmv.x.h. Keep the previous anyext opcode to allow the existing
(fmv_x_anyexth (fmv_h_x X)) combine to keep working without needing
to generate a sign extend.
For fmv.x.w we are able to match the sext_inreg in an isel pattern,
but a 16-bit sext_inreg is lowered to a shift pair before isel. This
seemed like a larger match than we should do in isel.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D118974
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4dc02065b81d5..3daf2d03de039 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1031,6 +1031,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setTargetDAGCombine(ISD::ROTL);
setTargetDAGCombine(ISD::ROTR);
setTargetDAGCombine(ISD::ANY_EXTEND);
+ if (Subtarget.hasStdExtZfh())
+ setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
if (Subtarget.hasStdExtF()) {
setTargetDAGCombine(ISD::ZERO_EXTEND);
setTargetDAGCombine(ISD::FP_TO_SINT);
@@ -7518,6 +7520,18 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG) {
return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false);
}
+static SDValue performSIGN_EXTEND_INREG(SDNode *N, SelectionDAG &DAG) {
+ SDValue Src = N->getOperand(0);
+
+ // Fold (sext_inreg (fmv_x_anyexth X), i16) -> (fmv_x_signexth X)
+ if (Src.getOpcode() == RISCVISD::FMV_X_ANYEXTH &&
+ cast<VTSDNode>(N->getOperand(1))->getVT().bitsGE(MVT::i16))
+ return DAG.getNode(RISCVISD::FMV_X_SIGNEXTH, SDLoc(N), N->getValueType(0),
+ Src.getOperand(0));
+
+ return SDValue();
+}
+
// Attempt to turn ANY_EXTEND into SIGN_EXTEND if the input to the ANY_EXTEND
// has users that require SIGN_EXTEND and the SIGN_EXTEND can be done for free
// by an instruction like ADDW/SUBW/MULW. Without this the ANY_EXTEND would be
@@ -8124,6 +8138,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
return performORCombine(N, DAG, Subtarget);
case ISD::XOR:
return performXORCombine(N, DAG);
+ case ISD::SIGN_EXTEND_INREG:
+ return performSIGN_EXTEND_INREG(N, DAG);
case ISD::ANY_EXTEND:
return performANY_EXTENDCombine(N, DCI, Subtarget);
case ISD::ZERO_EXTEND:
@@ -10540,6 +10556,7 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(FSR)
NODE_NAME_CASE(FMV_H_X)
NODE_NAME_CASE(FMV_X_ANYEXTH)
+ NODE_NAME_CASE(FMV_X_SIGNEXTH)
NODE_NAME_CASE(FMV_W_X_RV64)
NODE_NAME_CASE(FMV_X_ANYEXTW_RV64)
NODE_NAME_CASE(FCVT_X)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 6118d9be9ffff..8cd9b08c178a6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -75,6 +75,7 @@ enum NodeType : unsigned {
//
// FMV_H_X matches the semantics of the FMV.H.X.
// FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
+ // FMV_X_SIGNEXTH is similar to FMV.X.H and has a sign-extended result.
// FMV_W_X_RV64 matches the semantics of the FMV.W.X.
// FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
//
@@ -82,6 +83,7 @@ enum NodeType : unsigned {
// unnecessary GPR->FPR->GPR moves.
FMV_H_X,
FMV_X_ANYEXTH,
+ FMV_X_SIGNEXTH,
FMV_W_X_RV64,
FMV_X_ANYEXTW_RV64,
// FP to XLen int conversions. Corresponds to fcvt.l(u).s/d/h on RV64 and
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index a2753c1323548..6f6afb69c5d31 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -17,13 +17,15 @@
def SDT_RISCVFMV_H_X
: SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>;
-def SDT_RISCVFMV_X_ANYEXTH
+def SDT_RISCVFMV_X_EXTH
: SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>;
def riscv_fmv_h_x
: SDNode<"RISCVISD::FMV_H_X", SDT_RISCVFMV_H_X>;
def riscv_fmv_x_anyexth
- : SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_ANYEXTH>;
+ : SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_EXTH>;
+def riscv_fmv_x_signexth
+ : SDNode<"RISCVISD::FMV_X_SIGNEXTH", SDT_RISCVFMV_X_EXTH>;
//===----------------------------------------------------------------------===//
// Instructions
@@ -299,6 +301,7 @@ def : Pat<(any_fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>;
// Moves (no conversion)
def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;
def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>;
+def : Pat<(riscv_fmv_x_signexth FPR16:$src), (FMV_X_H FPR16:$src)>;
} // Predicates = [HasStdExtZfhOrZfhmin]
let Predicates = [HasStdExtZfh, IsRV32] in {
diff --git a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
index f6844b48c71b4..3f5de34309934 100644
--- a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
@@ -79,8 +79,6 @@ define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
; RV64IZFH-NEXT: fmv.x.h a0, ft0
-; RV64IZFH-NEXT: slli a0, a0, 48
-; RV64IZFH-NEXT: srai a0, a0, 48
; RV64IZFH-NEXT: ret
%1 = fadd half %a, %b
%2 = bitcast half %1 to i16
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