[PATCH] D119834: [RISCV] Add fixed-length vector instrinsics for segment load

[Luke via Phabricator via llvm-commits]

luke957 updated this revision to Diff 411120.
luke957 added a comment.

Address comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119834/new/

https://reviews.llvm.org/D119834

Files:
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll

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