[PATCH] D120467: [RISCV] Optimize (sext.w, srli) to sraiw with Zba.

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng created this revision.
Chenbing.Zheng added reviewers: craig.topper, frasercrmck, asb, benshi001.
Chenbing.Zheng added a project: LLVM.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Chenbing.Zheng requested review of this revision.
Herald added subscribers: llvm-commits, pcwang-thead, eopXD, jacquesguan, MaskRay.

In this patch, we add a more  narrower exclusion for 
zeroext (srl x)  -> srli (slli x), so that it provides an opportunity for the selection of sraiw.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120467

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll


Index: llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
+++ llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
@@ -1935,14 +1935,19 @@
   ret i32 %1
 }
 
-; TODO: The sext.w+srli can be replaced with sraiw with Zba.
 define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
-; RV64-LABEL: zext_sraiw_aext:
-; RV64:       # %bb.0:
-; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    slli a0, a0, 25
-; RV64-NEXT:    srli a0, a0, 32
-; RV64-NEXT:    ret
+; RV64I-LABEL: zext_sraiw_aext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    slli a0, a0, 25
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: zext_sraiw_aext:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sraiw a0, a0, 7
+; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    ret
   %1 = ashr i32 %a, 7
   ret i32 %1
 }
@@ -1957,14 +1962,19 @@
   ret i32 %1
 }
 
-; TODO: The sext.w+srli can be replaced with sraiw with Zba.
 define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
-; RV64-LABEL: zext_sraiw_zext:
-; RV64:       # %bb.0:
-; RV64-NEXT:    sext.w a0, a0
-; RV64-NEXT:    slli a0, a0, 23
-; RV64-NEXT:    srli a0, a0, 32
-; RV64-NEXT:    ret
+; RV64I-LABEL: zext_sraiw_zext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    slli a0, a0, 23
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: zext_sraiw_zext:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sraiw a0, a0, 9
+; RV64ZBA-NEXT:    zext.w a0, a0
+; RV64ZBA-NEXT:    ret
   %1 = ashr i32 %a, 9
   ret i32 %1
 }
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -769,7 +769,10 @@
         }
 
         // (srli (slli x, c3-c2), c3).
-        if (OneUseOrZExtW && !IsANDI) {
+        // Dealing with this situation, skip if has sext.w x with Zba.
+        bool Skip = Subtarget->hasStdExtZba() &&
+                    X.getOpcode() == ISD::SIGN_EXTEND_INREG;
+        if (OneUseOrZExtW && !IsANDI && !Skip) {
           SDNode *SLLI = CurDAG->getMachineNode(
               RISCV::SLLI, DL, XLenVT, X,
               CurDAG->getTargetConstant(C3 - C2, DL, XLenVT));


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D120467.411054.patch
Type: text/x-patch
Size: 2396 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220224/9b3e11f6/attachment.bin>