[llvm] e1d4d1c - [RISCV] Add schedule class for Zbm and Zbe extension

[Lian Wang via llvm-commits]

Author: lian wang
Date: 2022-02-24T08:49:25Z
New Revision: e1d4d1c2429fdcbc0387ab6b2d747efe07021a52

URL: https://github.com/llvm/llvm-project/commit/e1d4d1c2429fdcbc0387ab6b2d747efe07021a52
DIFF: https://github.com/llvm/llvm-project/commit/e1d4d1c2429fdcbc0387ab6b2d747efe07021a52.diff

LOG: [RISCV] Add schedule class for Zbm and Zbe extension

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D119805

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/lib/Target/RISCV/RISCVSchedRocket.td
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    llvm/lib/Target/RISCV/RISCVScheduleB.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 6d183a3a2e727..3b2e87802446d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -524,15 +524,19 @@ def MAXU : ALU_rr<0b0000101, 0b111, "maxu">,
 let Predicates = [HasStdExtZbe] in {
 // NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
 // bext in the 0.93 spec.
-def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
-def BCOMPRESS   : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
+def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">,
+                  Sched<[WriteDecompress, ReadDecompress, ReadDecompress]>;
+def BCOMPRESS   : ALU_rr<0b0000100, 0b110, "bcompress">,
+                  Sched<[WriteCompress, ReadCompress, ReadCompress]>;
 } // Predicates = [HasStdExtZbe]
 
 let Predicates = [HasStdExtZbe, IsRV64] in {
 // NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
 // bextw in the 0.93 spec.
-def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
-def BCOMPRESSW   : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
+def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">,
+                   Sched<[WriteDecompress32, ReadDecompress32, ReadDecompress32]>;
+def BCOMPRESSW   : ALUW_rr<0b0000100, 0b110, "bcompressw">,
+                   Sched<[WriteCompress32, ReadCompress32, ReadCompress32]>;
 } // Predicates = [HasStdExtZbe, IsRV64]
 
 let Predicates = [HasStdExtZbpOrZbkb] in {
@@ -551,10 +555,12 @@ def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
 
 let Predicates = [HasStdExtZbm, IsRV64] in {
 def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, OPC_OP_IMM, "bmatflip">,
-               Sched<[]>;
+               Sched<[WriteBMatrix, ReadBMatrix]>;
 
-def BMATOR   : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
-def BMATXOR  : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
+def BMATOR   : ALU_rr<0b0000100, 0b011, "bmator">,
+               Sched<[WriteBMatrix, ReadBMatrix, ReadBMatrix]>;
+def BMATXOR  : ALU_rr<0b0100100, 0b011, "bmatxor">,
+               Sched<[WriteBMatrix, ReadBMatrix, ReadBMatrix]>;
 } // Predicates = [HasStdExtZbm, IsRV64]
 
 let Predicates = [HasStdExtZbf] in

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
index 78cf34c8c582a..9f6501c017629 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -242,6 +242,8 @@ defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
+defm : UnsupportedSchedZbe;
 defm : UnsupportedSchedZbf;
+defm : UnsupportedSchedZbm;
 defm : UnsupportedSchedZfh;
 }

diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 9f5e5ff1223cd..26b7e08f1426a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -229,6 +229,8 @@ defm : UnsupportedSchedZba;
 defm : UnsupportedSchedZbb;
 defm : UnsupportedSchedZbc;
 defm : UnsupportedSchedZbs;
+defm : UnsupportedSchedZbe;
 defm : UnsupportedSchedZbf;
+defm : UnsupportedSchedZbm;
 defm : UnsupportedSchedZfh;
 }

diff  --git a/llvm/lib/Target/RISCV/RISCVScheduleB.td b/llvm/lib/Target/RISCV/RISCVScheduleB.td
index 193760e1e15b8..2a7d244e4fb73 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleB.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleB.td
@@ -33,10 +33,19 @@ def WriteCLMUL       : SchedWrite; // CLMUL/CLMULR/CLMULH
 def WriteSingleBit   : SchedWrite; // BCLR/BSET/BINV/BEXT
 def WriteSingleBitImm: SchedWrite; // BCLRI/BSETI/BINVI/BEXTI
 
+// Zbe extension
+def WriteDecompress  : SchedWrite; // bdecompress
+def WriteCompress    : SchedWrite; // bcompress
+def WriteDecompress32: SchedWrite; // bdecompressw
+def WriteCompress32  : SchedWrite; // bcompressw
+
 // Zbf extension
 def WriteBFP         : SchedWrite; // BFP
 def WriteBFP32       : SchedWrite; // BFPW
 
+// Zbm extension
+def WriteBMatrix     : SchedWrite; // bmator/bmatxor/bmatflip
+
 /// Define scheduler resources associated with use operands.
 
 // Zba extension
@@ -64,10 +73,19 @@ def ReadCLMUL       : SchedRead; // CLMUL/CLMULR/CLMULH
 def ReadSingleBit   : SchedRead; // BCLR/BSET/BINV/BEXT
 def ReadSingleBitImm: SchedRead; // BCLRI/BSETI/BINVI/BEXTI
 
+// Zbe extension
+def ReadDecompress  : SchedRead; // bdecompress
+def ReadCompress    : SchedRead; // bcompress
+def ReadDecompress32: SchedRead; // bdecompressw
+def ReadCompress32  : SchedRead; // bcompressw
+
 // Zbf extension
 def ReadBFP         : SchedRead; // BFP
 def ReadBFP32       : SchedRead; // BFPW
 
+// Zbm extension
+def ReadBMatrix     : SchedRead; // bmator/bmatxor/bmatflip
+
 /// Define default scheduler resources for B.
 
 multiclass UnsupportedSchedZba {
@@ -128,6 +146,20 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
 }
 }
 
+multiclass UnsupportedSchedZbe {
+let Unsupported = true in {
+def : WriteRes<WriteDecompress, []>;
+def : WriteRes<WriteCompress, []>;
+def : WriteRes<WriteDecompress32, []>;
+def : WriteRes<WriteCompress32, []>;
+
+def : ReadAdvance<ReadDecompress, 0>;
+def : ReadAdvance<ReadCompress, 0>;
+def : ReadAdvance<ReadDecompress32, 0>;
+def : ReadAdvance<ReadCompress32, 0>;
+}
+}
+
 multiclass UnsupportedSchedZbf {
 let Unsupported = true in {
 def : WriteRes<WriteBFP, []>;
@@ -137,3 +169,11 @@ def : ReadAdvance<ReadBFP, 0>;
 def : ReadAdvance<ReadBFP32, 0>;
 }
 }
+
+multiclass UnsupportedSchedZbm {
+let Unsupported = true in {
+def : WriteRes<WriteBMatrix, []>;
+
+def : ReadAdvance<ReadBMatrix, 0>;
+}
+}